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https://github.com/RT-Thread/rt-thread.git
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3d503e931b
Fix some code style and init for V2M, ITS. V2M is the PCI MSI/MSI-X for GICv2. ITS is the PCI MSI/MSI-X for GICv3/v4. Signed-off-by: GuEe-GUI <2991707448@qq.com>
60 lines
1.7 KiB
C
60 lines
1.7 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-01-30 GuEe-GUI first version
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*/
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#ifndef __PIC_GIC_COMMON_H__
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#define __PIC_GIC_COMMON_H__
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#include <rtdef.h>
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#ifdef RT_PCI_MSI
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#include <drivers/pci_msi.h>
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#endif
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#include <drivers/ofw.h>
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#define GIC_SGI_NR 16
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#define GICD_INT_DEF_PRI 0xa0U
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#define GICD_INT_DEF_PRI_X4 \
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( \
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(GICD_INT_DEF_PRI << 24) | \
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(GICD_INT_DEF_PRI << 16) | \
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(GICD_INT_DEF_PRI << 8) | \
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GICD_INT_DEF_PRI \
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)
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struct gic_quirk
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{
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const char *desc;
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const char *compatible;
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rt_err_t (*init)(void *data);
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rt_uint32_t iidr;
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rt_uint32_t iidr_mask;
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};
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void gic_common_init_quirk_ofw(const struct rt_ofw_node *ic_np, const struct gic_quirk *quirks, void *data);
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void gic_common_init_quirk_hw(rt_uint32_t iidr, const struct gic_quirk *quirks, void *data);
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void gic_common_sgi_config(void *base, void *data, int irq_base);
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rt_err_t gic_common_configure_irq(void *base, int irq, rt_uint32_t mode, void (*sync_access)(void *), void *data);
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void gic_common_dist_config(void *base, int max_irqs, void (*sync_access)(void *), void *data);
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void gic_common_cpu_config(void *base, int nr, void (*sync_access)(void *), void *data);
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void gic_fill_ppi_affinity(rt_bitmap_t *affinity);
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#ifdef RT_PIC_ARM_GIC_V2M
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rt_err_t gicv2m_ofw_probe(struct rt_ofw_node *ic_np, const struct rt_ofw_node_id *id);
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#endif
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#ifdef RT_PIC_ARM_GIC_V3_ITS
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rt_err_t gicv3_its_ofw_probe(struct rt_ofw_node *ic_np, const struct rt_ofw_node_id *id);
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#endif
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#endif /* __PIC_GIC_COMMON_H__ */
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