1064 lines
41 KiB
C
1064 lines
41 KiB
C
/**************************************************************************//**
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* @file pwm.c
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* @version V1.00
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* $Revision: 4 $
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* $Date: 18/04/25 11:43a $
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* @brief M031 series PWM driver source file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "NuMicro.h"
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/** @addtogroup Standard_Driver Standard Driver
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@{
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*/
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/** @addtogroup PWM_Driver PWM Driver
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@{
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*/
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/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
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@{
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*/
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/**
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* @brief Configure PWM capture and get the nearest unit time.
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* @param[in] pwm The pointer of the specified PWM module
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* - PWM0 : PWM Group 0
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* - PWM1 : PWM Group 1
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32UnitTimeNsec The unit time of counter
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* @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
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* @return The nearest unit time in nano second.
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* @details This function is used to Configure PWM capture and get the nearest unit time.
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*/
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uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
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{
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uint32_t u32Src;
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uint32_t u32PWMClockSrc;
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uint32_t u32NearestUnitTimeNsec;
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uint16_t u16Prescale = 1UL, u16CNR = 0xFFFFUL;
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uint8_t u8BreakLoop = 0UL;
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if (pwm == PWM0)
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u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk;
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else//(pwm == PWM1)
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u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk;
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if (u32Src == 0UL)
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{
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//clock source is from PLL clock
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u32PWMClockSrc = CLK_GetPLLClockFreq();
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}
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else
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{
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//clock source is from PCLK
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SystemCoreClockUpdate();
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if (pwm == PWM0)
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{
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u32PWMClockSrc = CLK_GetPCLK0Freq();
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}
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else /* (pwm == PWM1) */
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{
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u32PWMClockSrc = CLK_GetPCLK1Freq();
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}
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}
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u32PWMClockSrc /= 1000UL;
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for (u16Prescale = 1UL; u16Prescale <= 0x1000UL; u16Prescale++)
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{
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u32NearestUnitTimeNsec = (1000000UL * u16Prescale) / u32PWMClockSrc;
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if (u32NearestUnitTimeNsec < u32UnitTimeNsec)
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{
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if (u16Prescale == 0x1000UL)
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{
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/* limit to the maximum unit time(nano second) */
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u8BreakLoop = 1UL;
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}
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if (!((1000000UL * (u16Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc))))
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{
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u8BreakLoop = 1UL;
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}
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}
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else
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{
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u8BreakLoop = 1UL;
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}
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if (u8BreakLoop)
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{
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break;
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}
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}
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// convert to real register value
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u16Prescale = u16Prescale - 1UL;
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// every two channels share a prescaler
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PWM_SET_PRESCALER(pwm, u32ChannelNum, (uint32_t)u16Prescale);
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// set PWM to down count type(edge aligned)
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(pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << ((u32ChannelNum >> 1UL) << 2UL))) | (1UL << ((u32ChannelNum >> 1UL) << 2UL));
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PWM_SET_CNR(pwm, u32ChannelNum, u16CNR);
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return (u32NearestUnitTimeNsec);
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}
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/**
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* @brief This function Configure PWM generator and get the nearest frequency in edge aligned auto-reload mode
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* @param[in] pwm The pointer of the specified PWM module
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* - PWM0 : PWM Group 0
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* - PWM1 : PWM Group 1
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Frequency Target generator frequency
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* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
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* @return Nearest frequency clock in nano second
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* @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure PWM frequency may affect
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* existing frequency of other channel.
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*/
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uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
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{
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uint32_t u32Src;
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uint32_t u32PWMClockSrc;
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uint32_t i;
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uint16_t u16Prescale = 1UL, u16CNR = 0xFFFFUL;
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if (pwm == PWM0)
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u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk;
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else//(pwm == PWM1)
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u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk;
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if (u32Src == 0UL)
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{
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//clock source is from PLL clock
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u32PWMClockSrc = CLK_GetPLLClockFreq();
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}
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else
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{
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//clock source is from PCLK
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SystemCoreClockUpdate();
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if (pwm == PWM0)
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{
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u32PWMClockSrc = CLK_GetPCLK0Freq();
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}
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else /* (pwm == PWM1) */
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{
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u32PWMClockSrc = CLK_GetPCLK1Freq();
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}
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}
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for (u16Prescale = 1UL; u16Prescale < 0xFFFUL; u16Prescale++) //prescale could be 0~0xFFF
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{
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i = (u32PWMClockSrc / u32Frequency) / u16Prescale;
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// If target value is larger than CNR, need to use a larger prescaler
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if (i <= (0x10000UL))
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{
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u16CNR = (uint16_t)i;
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break;
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}
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}
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// Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register
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i = u32PWMClockSrc / ((uint32_t)u16Prescale * (uint32_t)u16CNR);
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// convert to real register value
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u16Prescale = u16Prescale - 1UL;
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// every two channels share a prescaler
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PWM_SET_PRESCALER(pwm, u32ChannelNum, (uint32_t)u16Prescale);
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// set PWM to down count type(edge aligned)
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(pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << ((u32ChannelNum >> 1UL) << 2UL))) | (1UL << ((u32ChannelNum >> 1UL) << 2UL));
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u16CNR -= 1UL;
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PWM_SET_CNR(pwm, u32ChannelNum, u16CNR);
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if (u32DutyCycle)
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{
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if (u32DutyCycle >= 100UL)
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PWM_SET_CMR(pwm, u32ChannelNum, u16CNR);
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else
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PWM_SET_CMR(pwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1UL) / 100UL);
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(pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1UL));
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(pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << ((u32ChannelNum << 1UL) + PWM_WGCTL0_PRDPCTL0_Pos));
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(pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1UL));
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(pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << ((u32ChannelNum << 1UL) + PWM_WGCTL1_CMPDCTL0_Pos));
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}
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else
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{
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PWM_SET_CMR(pwm, u32ChannelNum, 0UL);
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(pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1UL));
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(pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << ((u32ChannelNum << 1UL) + PWM_WGCTL0_ZPCTL0_Pos));
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(pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1UL));
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(pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << ((u32ChannelNum << 1UL) + PWM_WGCTL1_CMPDCTL0_Pos));
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}
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return (i);
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}
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/**
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* @brief Start PWM module
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* @param[in] pwm The pointer of the specified PWM module
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* - PWM0 : PWM Group 0
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* - PWM1 : PWM Group 1
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
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* Bit 0 is channel 0, bit 1 is channel 1...
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* @return None
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* @details This function is used to start PWM module.
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* @note Every two channels share the same setting.
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*/
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void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask)
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{
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uint32_t i;
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for (i = 0UL; i < PWM_CHANNEL_NUM; i ++)
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{
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if (u32ChannelMask & (1UL << i))
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{
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(pwm)->CNTEN |= (1UL << ((i >> 1UL) << 1UL));
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}
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}
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}
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/**
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* @brief Stop PWM module
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* @param[in] pwm The pointer of the specified PWM module
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* - PWM0 : PWM Group 0
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* - PWM1 : PWM Group 1
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
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* Bit 0 is channel 0, bit 1 is channel 1...
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* @return None
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* @details This function is used to stop PWM module.
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* @note Every two channels share the same setting.
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*/
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void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask)
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{
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uint32_t i;
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for (i = 0UL; i < PWM_CHANNEL_NUM; i ++)
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{
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if (u32ChannelMask & (1UL << i))
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{
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(pwm)->PERIOD[((i >> 1UL) << 1UL)] = 0UL;
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}
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}
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}
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/**
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* @brief Stop PWM generation immediately by clear channel enable bit
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* @param[in] pwm The pointer of the specified PWM module
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* - PWM0 : PWM Group 0
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* - PWM1 : PWM Group 1
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
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* Bit 0 is channel 0, bit 1 is channel 1...
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* @return None
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* @details This function is used to stop PWM generation immediately by clear channel enable bit.
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* @note Every two channels share the same setting.
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*/
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void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask)
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{
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uint32_t i;
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for (i = 0UL; i < PWM_CHANNEL_NUM; i ++)
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{
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if (u32ChannelMask & (1UL << i))
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{
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(pwm)->CNTEN &= ~(1UL << ((i >> 1UL) << 1UL));
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}
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}
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}
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/**
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* @brief Enable selected channel to trigger ADC
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* @param[in] pwm The pointer of the specified PWM module
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* - PWM0 : PWM Group 0
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* - PWM1 : PWM Group 1
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
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* - \ref PWM_TRIGGER_ADC_EVEN_ZERO_POINT
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* - \ref PWM_TRIGGER_ADC_EVEN_PERIOD_POINT
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* - \ref PWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT
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* - \ref PWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT
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* - \ref PWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT
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* - \ref PWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT
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* - \ref PWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT
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* @return None
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* @details This function is used to enable selected channel to trigger ADC.
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*/
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void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
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{
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if (u32ChannelNum < 4UL)
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{
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(pwm)->ADCTS0 &= ~((PWM_ADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3UL));
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(pwm)->ADCTS0 |= ((PWM_ADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3UL));
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}
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else
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{
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(pwm)->ADCTS1 &= ~((PWM_ADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4UL) << 3UL));
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(pwm)->ADCTS1 |= ((PWM_ADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4UL) << 3UL));
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}
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}
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/**
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* @brief Disable selected channel to trigger ADC
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* @param[in] pwm The pointer of the specified PWM module
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* - PWM0 : PWM Group 0
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* - PWM1 : PWM Group 1
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @return None
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* @details This function is used to disable selected channel to trigger ADC.
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*/
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void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum)
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{
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if (u32ChannelNum < 4UL)
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{
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(pwm)->ADCTS0 &= ~(PWM_ADCTS0_TRGEN0_Msk << (u32ChannelNum << 3UL));
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}
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else
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{
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(pwm)->ADCTS1 &= ~(PWM_ADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4UL) << 3UL));
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}
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}
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/**
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* @brief Clear selected channel trigger ADC flag
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* @param[in] pwm The pointer of the specified PWM module
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* - PWM0 : PWM Group 0
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* - PWM1 : PWM Group 1
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Condition This parameter is not used
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* @return None
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* @details This function is used to clear selected channel trigger ADC flag.
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*/
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void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
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{
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(pwm)->STATUS = (PWM_STATUS_ADCTRG0_Msk << u32ChannelNum);
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}
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/**
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* @brief Get selected channel trigger ADC flag
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* @param[in] pwm The pointer of the specified PWM module
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* - PWM0 : PWM Group 0
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* - PWM1 : PWM Group 1
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @retval 0 The specified channel trigger ADC to start of conversion flag is not set
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* @retval 1 The specified channel trigger ADC to start of conversion flag is set
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* @details This function is used to get PWM trigger ADC to start of conversion flag for specified channel.
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*/
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uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum)
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{
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return (((pwm)->STATUS & (PWM_STATUS_ADCTRG0_Msk << u32ChannelNum)) ? 1UL : 0UL);
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}
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/**
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* @brief This function enable fault brake of selected channel(s)
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* @param[in] pwm The pointer of the specified PWM module
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* - PWM0 : PWM Group 0
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* - PWM1 : PWM Group 1
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
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* @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel
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* while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1...
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* @param[in] u32BrakeSource Fault brake source, could be one of following source
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* - \ref PWM_FB_EDGE_ACMP0
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* - \ref PWM_FB_EDGE_ACMP1
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* - \ref PWM_FB_EDGE_BKP0
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* - \ref PWM_FB_EDGE_BKP1
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* - \ref PWM_FB_EDGE_SYS_CSS
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* - \ref PWM_FB_EDGE_SYS_BOD
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* - \ref PWM_FB_EDGE_SYS_COR
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* - \ref PWM_FB_LEVEL_ACMP0
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* - \ref PWM_FB_LEVEL_ACMP1
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* - \ref PWM_FB_LEVEL_BKP0
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* - \ref PWM_FB_LEVEL_BKP1
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* - \ref PWM_FB_LEVEL_SYS_CSS
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* - \ref PWM_FB_LEVEL_SYS_BOD
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* - \ref PWM_FB_LEVEL_SYS_COR
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* @return None
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* @details This function is used to enable fault brake of selected channel(s).
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* The write-protection function should be disabled before using this function.
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*/
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void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
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{
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uint32_t i;
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for (i = 0UL; i < PWM_CHANNEL_NUM; i ++)
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{
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if (u32ChannelMask & (1UL << i))
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{
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if ((u32BrakeSource == PWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == PWM_FB_EDGE_SYS_BOD) || \
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(u32BrakeSource == PWM_FB_EDGE_SYS_COR) || \
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(u32BrakeSource == PWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == PWM_FB_LEVEL_SYS_BOD) || \
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(u32BrakeSource == PWM_FB_LEVEL_SYS_COR))
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{
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(pwm)->BRKCTL[i >> 1UL] |= (u32BrakeSource & (PWM_BRKCTL_SYSEBEN_Msk | PWM_BRKCTL_SYSLBEN_Msk));
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(pwm)->FAILBRK |= (u32BrakeSource & 0xBUL);
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}
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else
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{
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(pwm)->BRKCTL[i >> 1UL] |= u32BrakeSource;
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}
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}
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if (u32LevelMask & (1UL << i))
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{
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if ((i & 0x1UL) == 0UL)
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{
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//set brake action as high level for even channel
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(pwm)->BRKCTL[i >> 1UL] &= ~PWM_BRKCTL0_1_BRKAEVEN_Msk;
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(pwm)->BRKCTL[i >> 1UL] |= ((3UL) << PWM_BRKCTL0_1_BRKAEVEN_Pos);
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}
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else
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{
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//set brake action as high level for odd channel
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(pwm)->BRKCTL[i >> 1UL] &= ~PWM_BRKCTL0_1_BRKAODD_Msk;
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(pwm)->BRKCTL[i >> 1UL] |= ((3UL) << PWM_BRKCTL0_1_BRKAODD_Pos);
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}
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}
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else
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{
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if ((i & 0x1UL) == 0UL)
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{
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//set brake action as low level for even channel
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(pwm)->BRKCTL[i >> 1UL] &= ~PWM_BRKCTL0_1_BRKAEVEN_Msk;
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(pwm)->BRKCTL[i >> 1UL] |= ((2UL) << PWM_BRKCTL0_1_BRKAEVEN_Pos);
|
|
}
|
|
else
|
|
{
|
|
//set brake action as low level for odd channel
|
|
(pwm)->BRKCTL[i >> 1UL] &= ~PWM_BRKCTL0_1_BRKAODD_Msk;
|
|
(pwm)->BRKCTL[i >> 1UL] |= ((2UL) << PWM_BRKCTL0_1_BRKAODD_Pos);
|
|
}
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief Enable capture of selected channel(s)
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
|
|
* Bit 0 is channel 0, bit 1 is channel 1...
|
|
* @return None
|
|
* @details This function is used to enable capture of selected channel(s).
|
|
*/
|
|
void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
|
|
{
|
|
(pwm)->CAPINEN |= u32ChannelMask;
|
|
(pwm)->CAPCTL |= u32ChannelMask;
|
|
}
|
|
|
|
/**
|
|
* @brief Disable capture of selected channel(s)
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
|
|
* Bit 0 is channel 0, bit 1 is channel 1...
|
|
* @return None
|
|
* @details This function is used to disable capture of selected channel(s).
|
|
*/
|
|
void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
|
|
{
|
|
(pwm)->CAPINEN &= ~u32ChannelMask;
|
|
(pwm)->CAPCTL &= ~u32ChannelMask;
|
|
}
|
|
|
|
/**
|
|
* @brief Enables PWM output generation of selected channel(s)
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
|
|
* Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
|
|
* @return None
|
|
* @details This function is used to enable PWM output generation of selected channel(s).
|
|
*/
|
|
void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
|
|
{
|
|
(pwm)->POEN |= u32ChannelMask;
|
|
}
|
|
|
|
/**
|
|
* @brief Disables PWM output generation of selected channel(s)
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
|
* Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
|
|
* @return None
|
|
* @details This function is used to disable PWM output generation of selected channel(s).
|
|
*/
|
|
void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
|
|
{
|
|
(pwm)->POEN &= ~u32ChannelMask;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable Dead zone of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
|
* @param[in] u32Duration Dead zone length in PWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone.
|
|
* @return None
|
|
* @details This function is used to enable Dead zone of selected channel.
|
|
* The write-protection function should be disabled before using this function.
|
|
* @note Every two channels share the same setting.
|
|
*/
|
|
void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
|
|
{
|
|
// every two channels share the same setting
|
|
(pwm)->DTCTL[(u32ChannelNum) >> 1UL] &= ~PWM_DTCTL0_1_DTCNT_Msk;
|
|
(pwm)->DTCTL[(u32ChannelNum) >> 1UL] |= PWM_DTCTL0_1_DTEN_Msk | u32Duration;
|
|
}
|
|
|
|
/**
|
|
* @brief Disable Dead zone of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
|
* @return None
|
|
* @details This function is used to disable Dead zone of selected channel.
|
|
* The write-protection function should be disabled before using this function.
|
|
*/
|
|
void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum)
|
|
{
|
|
// every two channels shares the same setting
|
|
(pwm)->DTCTL[(u32ChannelNum) >> 1UL] &= ~PWM_DTCTL0_1_DTEN_Msk;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable capture interrupt of selected channel.
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
|
* @param[in] u32Edge Rising or falling edge to latch counter.
|
|
* - \ref PWM_CAPTURE_INT_RISING_LATCH
|
|
* - \ref PWM_CAPTURE_INT_FALLING_LATCH
|
|
* @return None
|
|
* @details This function is used to enable capture interrupt of selected channel.
|
|
*/
|
|
void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
|
|
{
|
|
(pwm)->CAPIEN |= (u32Edge << u32ChannelNum);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable capture interrupt of selected channel.
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
|
* @param[in] u32Edge Rising or falling edge to latch counter.
|
|
* - \ref PWM_CAPTURE_INT_RISING_LATCH
|
|
* - \ref PWM_CAPTURE_INT_FALLING_LATCH
|
|
* @return None
|
|
* @details This function is used to disable capture interrupt of selected channel.
|
|
*/
|
|
void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
|
|
{
|
|
(pwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear capture interrupt of selected channel.
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
|
* @param[in] u32Edge Rising or falling edge to latch counter.
|
|
* - \ref PWM_CAPTURE_INT_RISING_LATCH
|
|
* - \ref PWM_CAPTURE_INT_FALLING_LATCH
|
|
* @return None
|
|
* @details This function is used to clear capture interrupt of selected channel.
|
|
*/
|
|
void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
|
|
{
|
|
(pwm)->CAPIF = (u32Edge << u32ChannelNum);
|
|
}
|
|
|
|
/**
|
|
* @brief Get capture interrupt of selected channel.
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
|
* @retval 0 No capture interrupt
|
|
* @retval 1 Rising edge latch interrupt
|
|
* @retval 2 Falling edge latch interrupt
|
|
* @retval 3 Rising and falling latch interrupt
|
|
* @details This function is used to get capture interrupt of selected channel.
|
|
*/
|
|
uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
|
|
{
|
|
uint32_t u32CapFFlag, u32CapRFlag ;
|
|
u32CapFFlag = (((pwm)->CAPIF & (PWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) ;
|
|
u32CapRFlag = (((pwm)->CAPIF & (PWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) ;
|
|
return ((u32CapFFlag << 1UL) | u32CapRFlag);
|
|
}
|
|
/**
|
|
* @brief Enable duty interrupt of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
|
* @param[in] u32IntDutyType Duty interrupt type, could be either
|
|
* - \ref PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
|
|
* - \ref PWM_DUTY_INT_UP_COUNT_MATCH_CMP
|
|
* @return None
|
|
* @details This function is used to enable duty interrupt of selected channel.
|
|
*/
|
|
void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
|
|
{
|
|
(pwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable duty interrupt of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
|
* @return None
|
|
* @details This function is used to disable duty interrupt of selected channel.
|
|
*/
|
|
void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum)
|
|
{
|
|
(pwm)->INTEN0 &= ~((PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | PWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear duty interrupt flag of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
|
* @return None
|
|
* @details This function is used to clear duty interrupt flag of selected channel.
|
|
*/
|
|
void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
|
|
{
|
|
(pwm)->INTSTS0 = (PWM_INTSTS0_CMPUIF0_Msk | PWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum;
|
|
}
|
|
|
|
/**
|
|
* @brief Get duty interrupt flag of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
|
* @return Duty interrupt flag of specified channel
|
|
* @retval 0 Duty interrupt did not occur
|
|
* @retval 1 Duty interrupt occurred
|
|
* @details This function is used to get duty interrupt flag of selected channel.
|
|
*/
|
|
uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
|
|
{
|
|
return ((((pwm)->INTSTS0 & ((PWM_INTSTS0_CMPDIF0_Msk | PWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1 : 0);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable load mode of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
|
* @param[in] u32LoadMode PWM counter loading mode.
|
|
* - \ref PWM_LOAD_MODE_IMMEDIATE
|
|
* - \ref PWM_LOAD_MODE_CENTER
|
|
* @return None
|
|
* @details This function is used to enable load mode of selected channel.
|
|
*/
|
|
void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
|
|
{
|
|
(pwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable load mode of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
|
* @param[in] u32LoadMode PWM counter loading mode.
|
|
* - \ref PWM_LOAD_MODE_IMMEDIATE
|
|
* - \ref PWM_LOAD_MODE_CENTER
|
|
* @return None
|
|
* @details This function is used to disable load mode of selected channel.
|
|
*/
|
|
void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
|
|
{
|
|
(pwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
|
|
}
|
|
|
|
/**
|
|
* @brief This function enable fault brake interrupt
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* @param[in] u32BrakeSource Fault brake source.
|
|
* - \ref PWM_FB_EDGE
|
|
* - \ref PWM_FB_LEVEL
|
|
* @return None
|
|
* @details This function is used to enable fault brake interrupt.
|
|
* The write-protection function should be disabled before using this function.
|
|
* @note Every two channels share the same setting.
|
|
*/
|
|
void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
|
|
{
|
|
(pwm)->INTEN1 |= (0x7UL << u32BrakeSource);
|
|
}
|
|
|
|
/**
|
|
* @brief This function disable fault brake interrupt
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* @param[in] u32BrakeSource Fault brake source.
|
|
* - \ref PWM_FB_EDGE
|
|
* - \ref PWM_FB_LEVEL
|
|
* @return None
|
|
* @details This function is used to disable fault brake interrupt.
|
|
* The write-protection function should be disabled before using this function.
|
|
* @note Every two channels share the same setting.
|
|
*/
|
|
void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
|
|
{
|
|
(pwm)->INTEN1 &= ~(0x7UL << u32BrakeSource);
|
|
}
|
|
|
|
/**
|
|
* @brief This function clear fault brake interrupt of selected source
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* @param[in] u32BrakeSource Fault brake source.
|
|
* - \ref PWM_FB_EDGE
|
|
* - \ref PWM_FB_LEVEL
|
|
* @return None
|
|
* @details This function is used to clear fault brake interrupt of selected source.
|
|
* The write-protection function should be disabled before using this function.
|
|
*/
|
|
void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
|
|
{
|
|
(pwm)->INTSTS1 = (0x3fUL << u32BrakeSource);
|
|
}
|
|
|
|
/**
|
|
* @brief This function get fault brake interrupt flag of selected source
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* @param[in] u32BrakeSource Fault brake source, could be either
|
|
* - \ref PWM_FB_EDGE
|
|
* - \ref PWM_FB_LEVEL
|
|
* @return Fault brake interrupt flag of specified source
|
|
* @retval 0 Fault brake interrupt did not occurred
|
|
* @retval 1 Fault brake interrupt occurred
|
|
* @details This function is used to get fault brake interrupt flag of selected source.
|
|
*/
|
|
uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
|
|
{
|
|
return (((pwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable period interrupt of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting.
|
|
* @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.
|
|
* @return None
|
|
* @details This function is used to enable period interrupt of selected channel.
|
|
*/
|
|
void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
|
|
{
|
|
(pwm)->INTEN0 |= (PWM_INTEN0_PIEN0_Msk << ((u32ChannelNum >> 1UL) << 1UL));
|
|
}
|
|
|
|
/**
|
|
* @brief Disable period interrupt of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting.
|
|
* @return None
|
|
* @details This function is used to disable period interrupt of selected channel.
|
|
*/
|
|
void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum)
|
|
{
|
|
(pwm)->INTEN0 &= ~(PWM_INTEN0_PIEN0_Msk << ((u32ChannelNum >> 1UL) << 1UL));
|
|
}
|
|
|
|
/**
|
|
* @brief Clear period interrupt of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting.
|
|
* @return None
|
|
* @details This function is used to clear period interrupt of selected channel.
|
|
*/
|
|
void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
|
|
{
|
|
(pwm)->INTSTS0 = (PWM_INTSTS0_PIF0_Msk << ((u32ChannelNum >> 1UL) << 1UL));
|
|
}
|
|
|
|
/**
|
|
* @brief Get period interrupt of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting.
|
|
* @return Period interrupt flag of specified channel
|
|
* @retval 0 Period interrupt did not occur
|
|
* @retval 1 Period interrupt occurred
|
|
* @details This function is used to get period interrupt of selected channel.
|
|
*/
|
|
uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
|
|
{
|
|
return (((pwm)->INTSTS0 & (PWM_INTSTS0_PIF0_Msk << ((u32ChannelNum >> 1UL) << 1UL))) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable zero interrupt of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting.
|
|
* @return None
|
|
* @details This function is used to enable zero interrupt of selected channel.
|
|
*/
|
|
void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
|
|
{
|
|
(pwm)->INTEN0 |= (PWM_INTEN0_ZIEN0_Msk << ((u32ChannelNum >> 1UL) << 1UL));
|
|
}
|
|
|
|
/**
|
|
* @brief Disable zero interrupt of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting.
|
|
* @return None
|
|
* @details This function is used to disable zero interrupt of selected channel.
|
|
*/
|
|
void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
|
|
{
|
|
(pwm)->INTEN0 &= ~(PWM_INTEN0_ZIEN0_Msk << ((u32ChannelNum >> 1UL) << 1UL));
|
|
}
|
|
|
|
/**
|
|
* @brief Clear zero interrupt of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
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* - PWM0 : PWM Group 0
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* - PWM1 : PWM Group 1
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting.
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* @return None
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* @details This function is used to clear zero interrupt of selected channel.
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|
*/
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void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
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{
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(pwm)->INTSTS0 = (PWM_INTSTS0_ZIF0_Msk << ((u32ChannelNum >> 1UL) << 1UL));
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}
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/**
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* @brief Get zero interrupt of selected channel
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* @param[in] pwm The pointer of the specified PWM module
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* - PWM0 : PWM Group 0
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* - PWM1 : PWM Group 1
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting.
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* @return zero interrupt flag of specified channel
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* @retval 0 zero interrupt did not occur
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* @retval 1 zero interrupt occurred
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* @details This function is used to get zero interrupt of selected channel.
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|
*/
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uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
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|
{
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return (((pwm)->INTSTS0 & (PWM_INTSTS0_ZIF0_Msk << ((u32ChannelNum >> 1UL) << 1UL))) ? 1UL : 0UL);
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}
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/**
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* @brief Set PWM clock source
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* @param[in] pwm The pointer of the specified PWM module
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* - PWM0 : PWM Group 0
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* - PWM1 : PWM Group 1
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32ClkSrcSel PWM external clock source.
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* - \ref PWM_CLKSRC_PWM_CLK
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* - \ref PWM_CLKSRC_TIMER0
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* - \ref PWM_CLKSRC_TIMER1
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* - \ref PWM_CLKSRC_TIMER2
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* - \ref PWM_CLKSRC_TIMER3
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* @return None
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* @details This function is used to set PWM clock source.
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* @note Every two channels share the same setting.
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|
*/
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void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
|
|
{
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(pwm)->CLKSRC = ((pwm)->CLKSRC & ~(PWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1UL) * PWM_CLKSRC_ECLKSRC2_Pos))) | \
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(u32ClkSrcSel << ((u32ChannelNum >> 1UL) * PWM_CLKSRC_ECLKSRC2_Pos));
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}
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|
|
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/**
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|
* @brief Enable PWM brake noise filter function
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|
* @param[in] pwm The pointer of the specified PWM module
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* - PWM0 : PWM Group 0
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* - PWM1 : PWM Group 1
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|
* @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
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|
* @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector
|
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* @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
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|
* - \ref PWM_NF_CLK_DIV_1
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|
* - \ref PWM_NF_CLK_DIV_2
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|
* - \ref PWM_NF_CLK_DIV_4
|
|
* - \ref PWM_NF_CLK_DIV_8
|
|
* - \ref PWM_NF_CLK_DIV_16
|
|
* - \ref PWM_NF_CLK_DIV_32
|
|
* - \ref PWM_NF_CLK_DIV_64
|
|
* - \ref PWM_NF_CLK_DIV_128
|
|
* @return None
|
|
* @details This function is used to enable PWM brake noise filter function.
|
|
*/
|
|
void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
|
|
{
|
|
(pwm)->BNF = ((pwm)->BNF & ~((PWM_BNF_BRK0FCNT_Msk | PWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos))) | \
|
|
(((u32ClkCnt << PWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << PWM_BNF_BRK0NFSEL_Pos) | PWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
|
|
}
|
|
|
|
/**
|
|
* @brief Disable PWM brake noise filter function
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
|
|
* @return None
|
|
* @details This function is used to disable PWM brake noise filter function.
|
|
*/
|
|
void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum)
|
|
{
|
|
(pwm)->BNF &= ~(PWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
|
|
}
|
|
|
|
/**
|
|
* @brief Enable PWM brake pin inverse function
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
|
|
* @return None
|
|
* @details This function is used to enable PWM brake pin inverse function.
|
|
*/
|
|
void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
|
|
{
|
|
(pwm)->BNF |= (PWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
|
|
}
|
|
|
|
/**
|
|
* @brief Disable PWM brake pin inverse function
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
|
|
* @return None
|
|
* @details This function is used to disable PWM brake pin inverse function.
|
|
*/
|
|
void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
|
|
{
|
|
(pwm)->BNF &= ~(PWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
|
|
}
|
|
|
|
/**
|
|
* @brief Set PWM brake pin source
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
|
|
* @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE.
|
|
* @return None
|
|
* @details This function is used to set PWM brake pin source.
|
|
*/
|
|
void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule)
|
|
{
|
|
(pwm)->BNF = ((pwm)->BNF & ~(PWM_BNF_BK0SRC_Msk << (u32BrakePinNum << 3UL))) | (u32SelAnotherModule << (PWM_BNF_BK0SRC_Pos + (u32BrakePinNum << 3UL)));
|
|
}
|
|
|
|
/**
|
|
* @brief Get the time-base counter reached its maximum value flag of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting.
|
|
* @return Count to max interrupt flag of specified channel
|
|
* @retval 0 Count to max interrupt did not occur
|
|
* @retval 1 Count to max interrupt occurred
|
|
* @details This function is used to get the time-base counter reached its maximum value flag of selected channel.
|
|
*/
|
|
uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
|
|
{
|
|
return (((pwm)->STATUS & (PWM_STATUS_CNTMAX0_Msk << ((u32ChannelNum >> 1UL) << 1UL))) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear the time-base counter reached its maximum value flag of selected channel
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting.
|
|
* @return None
|
|
* @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.
|
|
*/
|
|
void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
|
|
{
|
|
(pwm)->STATUS = (PWM_STATUS_CNTMAX0_Msk << ((u32ChannelNum >> 1UL) << 1UL));
|
|
}
|
|
|
|
/**
|
|
* @brief Enables PDMA transfer of selected channel for PWM capture
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number.
|
|
* @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE.
|
|
* @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either
|
|
* - \ref PWM_CAPTURE_PDMA_RISING_LATCH
|
|
* - \ref PWM_CAPTURE_PDMA_FALLING_LATCH
|
|
* - \ref PWM_CAPTURE_PDMA_RISING_FALLING_LATCH
|
|
* @return None
|
|
* @details This function is used to enable PDMA transfer of selected channel(s) for PWM capture.
|
|
* @note This function can only selects even or odd channel of pairs to do PDMA transfer.
|
|
*/
|
|
void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
|
|
{
|
|
uint32_t u32IsOddCh;
|
|
u32IsOddCh = u32ChannelNum % 2UL;
|
|
(pwm)->PDMACTL = ((pwm)->PDMACTL & ~((PWM_PDMACTL_CHSEL0_1_Msk | PWM_PDMACTL_CAPORD0_1_Msk | PWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1UL) << 3UL))) | \
|
|
(((u32IsOddCh << PWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << PWM_PDMACTL_CAPORD0_1_Pos) | \
|
|
u32Mode | PWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1UL) << 3UL));
|
|
}
|
|
|
|
/**
|
|
* @brief Disables PDMA transfer of selected channel for PWM capture
|
|
* @param[in] pwm The pointer of the specified PWM module
|
|
* - PWM0 : PWM Group 0
|
|
* - PWM1 : PWM Group 1
|
|
* @param[in] u32ChannelNum PWM channel number.
|
|
* @return None
|
|
* @details This function is used to enable PDMA transfer of selected channel(s) for PWM capture.
|
|
*/
|
|
void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum)
|
|
{
|
|
(pwm)->PDMACTL &= ~(PWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1UL) << 3UL));
|
|
}
|
|
|
|
/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
|
|
|
|
/*@}*/ /* end of group PWM_Driver */
|
|
|
|
/*@}*/ /* end of group Standard_Driver */
|
|
|
|
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|