211 lines
6.1 KiB
C
211 lines
6.1 KiB
C
/*""FILE COMMENT""*******************************************************
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* System Name : BSC API for RX62Nxx
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* File Name : r_pdl_bsc.h
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* Version : 1.02
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* Contents : BSC API header
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* Customer :
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* Model :
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* Order :
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* CPU : RX
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* Compiler : RXC
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* OS : Nothing
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* Programmer :
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* Note :
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************************************************************************
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* Copyright, 2011. Renesas Electronics Corporation
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* and Renesas Solutions Corporation
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************************************************************************
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* History : 2011.04.08
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* : Ver 1.02
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* : CS-5 release.
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*""FILE COMMENT END""**************************************************/
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#ifndef R_PDL_BSC_H
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#define R_PDL_BSC_H
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#include "r_pdl_common_defs_RX62Nxx.h"
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/* Function prototypes */
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bool R_BSC_Create(
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uint32_t,
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uint32_t,
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uint8_t,
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void *,
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uint8_t
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);
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bool R_BSC_CreateArea(
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uint8_t,
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uint16_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t
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);
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bool R_BSC_SDRAM_CreateArea(
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uint16_t,
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uint16_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint16_t
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);
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bool R_BSC_Destroy(
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uint8_t
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);
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bool R_BSC_Control(
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uint16_t
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);
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bool R_BSC_GetStatus(
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uint8_t *,
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uint16_t *,
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uint8_t *
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);
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/* R_BSC_Create parameter options */
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/* Configuration1 (pin select control) */
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/* Chip select pin selection */
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#define PDL_BSC_CS0_A 0x00000001ul
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#define PDL_BSC_CS0_B 0x00000002ul
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#define PDL_BSC_CS1_A 0x00000004ul
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#define PDL_BSC_CS1_B 0x00000008ul
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#define PDL_BSC_CS1_C 0x00000010ul
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#define PDL_BSC_CS2_A 0x00000020ul
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#define PDL_BSC_CS2_B 0x00000040ul
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#define PDL_BSC_CS2_C 0x00000080ul
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#define PDL_BSC_CS3_A 0x00000100ul
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#define PDL_BSC_CS3_B 0x00000200ul
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#define PDL_BSC_CS3_C 0x00000400ul
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#define PDL_BSC_CS4_A 0x00000800ul
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#define PDL_BSC_CS4_B 0x00001000ul
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#define PDL_BSC_CS4_C 0x00002000ul
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#define PDL_BSC_CS5_A 0x00004000ul
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#define PDL_BSC_CS5_B 0x00008000ul
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#define PDL_BSC_CS5_C 0x00010000ul
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#define PDL_BSC_CS6_A 0x00020000ul
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#define PDL_BSC_CS6_B 0x00040000ul
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#define PDL_BSC_CS6_C 0x00080000ul
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#define PDL_BSC_CS7_A 0x00100000ul
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#define PDL_BSC_CS7_B 0x00200000ul
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#define PDL_BSC_CS7_C 0x00400000ul
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/* Address (A23-A16) pin selection */
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#define PDL_BSC_A23_A16_A 0x00800000ul
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#define PDL_BSC_A23_A16_B 0x01000000ul
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/* WAIT pin selection */
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#define PDL_BSC_WAIT_NOT_USED 0x02000000ul
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#define PDL_BSC_WAIT_A 0x04000000ul
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#define PDL_BSC_WAIT_B 0x08000000ul
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#define PDL_BSC_WAIT_C 0x10000000ul
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#define PDL_BSC_WAIT_D 0x20000000ul
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/* Configuration2 (output enable control) */
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/* Address output control */
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#define PDL_BSC_A9_A0_DISABLE 0x00000001ul
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#define PDL_BSC_A9_A4_DISABLE 0x00000002ul
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#define PDL_BSC_A9_A8_DISABLE 0x00000004ul
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#define PDL_BSC_A10_DISABLE 0x00000008ul
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#define PDL_BSC_A11_DISABLE 0x00000010ul
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#define PDL_BSC_A12_DISABLE 0x00000020ul
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#define PDL_BSC_A13_DISABLE 0x00000040ul
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#define PDL_BSC_A14_DISABLE 0x00000080ul
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#define PDL_BSC_A15_DISABLE 0x00000100ul
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#define PDL_BSC_A16_DISABLE 0x00000200ul
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#define PDL_BSC_A17_DISABLE 0x00000400ul
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#define PDL_BSC_A18_DISABLE 0x00000800ul
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#define PDL_BSC_A19_DISABLE 0x00001000ul
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#define PDL_BSC_A20_DISABLE 0x00002000ul
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#define PDL_BSC_A21_DISABLE 0x00004000ul
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#define PDL_BSC_A22_DISABLE 0x00008000ul
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#define PDL_BSC_A23_DISABLE 0x00010000ul
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/* SDRAM output control */
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#define PDL_BSC_SDRAM_PINS_DISABLE 0x00020000ul
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#define PDL_BSC_SDRAM_PINS_ENABLE 0x00040000ul
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#define PDL_BSC_SDRAM_DQM1_DISABLE 0x00080000ul
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#define PDL_BSC_SDRAM_DQM1_ENABLE 0x00100000ul
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/* Configuration3 (error control) */
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/* Error monitoring */
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#define PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE 0x01u
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#define PDL_BSC_ERROR_ILLEGAL_ADDRESS_DISABLE 0x02u
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#define PDL_BSC_ERROR_TIME_OUT_ENABLE 0x04u
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#define PDL_BSC_ERROR_TIME_OUT_DISABLE 0x08u
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/* R_BSC_CreateArea parameter options */
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/* Configuration selection */
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/* Bus width */
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#define PDL_BSC_WIDTH_16 0x0001u
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#define PDL_BSC_WIDTH_8 0x0002u
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#define PDL_BSC_WIDTH_32 0x0004u
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/* Endian mode */
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#define PDL_BSC_ENDIAN_SAME 0x0008u
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#define PDL_BSC_ENDIAN_OPPOSITE 0x0010u
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/* Write access mode */
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#define PDL_BSC_WRITE_BYTE 0x0020u
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#define PDL_BSC_WRITE_SINGLE 0x0040u
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/* External wait control */
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#define PDL_BSC_WAIT_DISABLE 0x0080u
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#define PDL_BSC_WAIT_ENABLE 0x0100u
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/* Page access control */
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#define PDL_BSC_PAGE_READ_DISABLE 0x0200u
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#define PDL_BSC_PAGE_READ_NORMAL 0x0400u
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#define PDL_BSC_PAGE_READ_CONTINUOUS 0x0800u
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#define PDL_BSC_PAGE_WRITE_DISABLE 0x1000u
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#define PDL_BSC_PAGE_WRITE_ENABLE 0x2000u
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/* R_BSC_Control parameter options */
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#define PDL_BSC_ERROR_CLEAR 0x0001u
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#define PDL_BSC_SDRAM_INITIALIZATION 0x0002u
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#define PDL_BSC_SDRAM_AUTO_REFRESH_ENABLE 0x0004u
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#define PDL_BSC_SDRAM_AUTO_REFRESH_DISABLE 0x0008u
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#define PDL_BSC_SDRAM_SELF_REFRESH_ENABLE 0x0010u
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#define PDL_BSC_SDRAM_SELF_REFRESH_DISABLE 0x0020u
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#define PDL_BSC_SDRAM_ENABLE 0x0040u
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#define PDL_BSC_SDRAM_DISABLE 0x0080u
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#define PDL_BSC_DISABLE_BUSERR_IRQ 0x0100u
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/* R_BSC_SDRAM_CreateArea parameter options */
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/* Configuration selection */
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/* Bus width */
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#define PDL_BSC_SDRAM_WIDTH_16 0x0001u
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#define PDL_BSC_SDRAM_WIDTH_8 0x0002u
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#define PDL_BSC_SDRAM_WIDTH_32 0x0004u
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/* Endian mode */
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#define PDL_BSC_SDRAM_ENDIAN_SAME 0x0008u
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#define PDL_BSC_SDRAM_ENDIAN_OPPOSITE 0x0010u
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/* Continuous access mode */
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#define PDL_BSC_SDRAM_CONT_ACCESS_ENABLE 0x0020u
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#define PDL_BSC_SDRAM_CONT_ACCESS_DISABLE 0x0040u
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/* Address multiplex selection */
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#define PDL_BSC_SDRAM_8_BIT_SHIFT 0x0080u
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#define PDL_BSC_SDRAM_9_BIT_SHIFT 0x0100u
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#define PDL_BSC_SDRAM_10_BIT_SHIFT 0x0200u
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#define PDL_BSC_SDRAM_11_BIT_SHIFT 0x0400u
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#endif
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/* End of file */
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