291 lines
5.7 KiB
C
291 lines
5.7 KiB
C
/*
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* File : cpu.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2013-7-14 Peng Fan sep6200 implementation
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <sep6200.h>
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/**
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* @addtogroup sep6200
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*/
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/*@{*/
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#ifdef __GNUC__
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rt_inline void cache_invalid(void)
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{
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__asm__ volatile ("movc p0.c5, r1, #28\n"
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"nop;nop;nop;nop;nop;nop;nop;nop;\n"
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:
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:
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:"memory", "cc"
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);
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}
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rt_inline void cache_enable(void)
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{
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__asm__ volatile ( "movc r1, p0.c1, #0\n"
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"or r1, r1, #0xc\n"
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"movc p0.c1, r1, #0\n"
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"nop;nop;nop;nop;nop;nop;nop;nop;\n"
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:
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:
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:"r0", "memory", "cc");
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}
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rt_inline void clean_dcache(void)
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{
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__asm__ volatile ( "mov ip, #0\n"
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"movc p0.c5, ip, #10\n"
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"nop; nop; nop; nop; nop; nop; nop; nop\n"
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:
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:
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:"ip", "memory", "cc");
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}
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rt_inline rt_uint32_t icache_status(void)
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{
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rt_uint32_t ret;
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__asm__ volatile ( "movc %0, p0.c1, #0\n"
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"and %0, %0, #8\n"
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: "=&r" (ret)
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:
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:"memory", "cc");
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return ret;
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}
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rt_inline rt_uint32_t dcache_status(void)
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{
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rt_uint32_t ret;
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__asm__ volatile ( "movc %0, p0.c1, #0\n"
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"and %0, %0, #4\n"
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: "=&r" (ret)
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:
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:"memory", "cc");
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return ret;
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}
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rt_inline void dcache_flush(void)
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{
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__asm__ volatile ( "mov ip, #0\n"
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"movc p0.c5, ip, #14\n"
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"nop; nop; nop; nop; nop; nop; nop; nop\n"
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:
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:
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: "ip" );
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}
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rt_inline void icache_invalid(void)
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{
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__asm__ volatile ( "mov r0, #0\n"
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"movc p0.c5, r0, #20\n"
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"nop; nop; nop; nop; nop; nop; nop; nop\n"
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:
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:
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:"r0", "memory", "cc");
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}
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rt_inline void dcache_invalid(void)
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{
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__asm__ volatile ( "mov r0, #0\n"
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"movc p0.c5, r0, #12\n"
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"nop; nop; nop; nop; nop; nop; nop; nop\n"
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:
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:
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:"r0", "memory", "cc");
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}
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rt_inline void icache_disable(void)
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{
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icache_invalid();
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__asm__ volatile ( "movc r0, p0.c1, #0\n"
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"andn r0, r0, #8\n"
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"movc p0.c1, r0, #0\n"
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:
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:
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:"r0", "memory", "cc");
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}
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rt_inline void dcache_disable(void)
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{
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dcache_flush();
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__asm__ volatile ( "movc r0, p0.c1, #0\n"
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"andn r0, r0, #20\n"
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"movc p0.c1, r0, #0\n"
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:
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:
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:"r0", "memory", "cc");
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}
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rt_inline void icache_enable(void)
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{
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__asm__ volatile ( "mov r0, #0\n"
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"movc p0.c5, r0, #20\n"
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"nop; nop; nop; nop; nop; nop; nop; nop\n"
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:
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:
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:"r0", "memory", "cc");
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__asm__ volatile ( "movc r0, p0.c1, #0\n"
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"or r0, r0, #8\n"
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"movc p0.c1, r0, #0\n"
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:
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:
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:"r0", "memory", "cc");
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}
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rt_inline void dcache_enable(void)
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{
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__asm__ volatile ( "mov r0, #0\n"
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"movc p0.c5, r0, #12\n"
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"nop; nop; nop; nop; nop; nop; nop; nop\n"
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:
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:
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:"r0", "memory", "cc");
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__asm__ volatile ( "movc r0, p0.c1, #0\n"
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"or r0, r0, #20\n"
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"movc p0.c1, r0, #0\n"
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:
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:
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:"r0", "memory", "cc");
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}
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#endif
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/**
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* enable I-Cache
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*
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*/
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void rt_hw_cpu_icache_enable()
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{
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icache_enable();
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}
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/**
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* disable I-Cache
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*
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*/
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void rt_hw_cpu_icache_disable()
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{
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icache_disable();
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}
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/**
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* return the status of I-Cache
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*
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*/
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rt_base_t rt_hw_cpu_icache_status()
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{
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return icache_status();
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}
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/**
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* enable D-Cache
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*
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*/
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void rt_hw_cpu_dcache_enable()
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{
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dcache_enable();
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}
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/**
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* disable D-Cache
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*
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*/
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void rt_hw_cpu_dcache_disable()
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{
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dcache_disable();
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}
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/**
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* return the status of D-Cache
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*
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*/
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rt_base_t rt_hw_cpu_dcache_status()
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{
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return dcache_status();
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}
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static void sep6200_reset(rt_uint32_t addr)
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{
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__asm__ volatile ( "mov ip, #0\n"
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"movc p0.c5, ip, #28\n" /*Cache invalidate all*/
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"movc p0.c6, ip, #6\n" /*TLB invalidate all*/
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"nop;nop;nop;nop;nop;nop;nop;nop;\n"
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"movc ip, p0.c1, #0\n" /*ctrl register*/
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"andn ip, ip, #0x000f\n" /*disable caches and mmu*/
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"movc p0.c1, ip, #0\n"
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"nop\n"
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"mov pc, %0\n"
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"nop;nop;nop;nop;nop;nop;nop;nop;\n"
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: "=&r" (addr)
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:
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:"memory", "cc");
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}
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static void sep6200_poweroff(void)
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{
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rt_kprintf("sep6200 power off not implemented\n");
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while(1);
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}
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/**
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* reset cpu by dog's time-out
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*
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*/
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RT_WEAK void rt_hw_cpu_reset()
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{
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rt_kprintf("Soft reset, Restarting system...\n");
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sep6200_reset(0);
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while(1); /* loop forever and wait for reset to happen */
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/* NEVER REACHED */
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}
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/**
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* shutdown CPU
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*
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*/
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RT_WEAK void rt_hw_cpu_shutdown()
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{
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rt_uint32_t level;
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rt_kprintf("shutdown...\n");
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level = rt_hw_interrupt_disable();
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sep6200_poweroff();
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while (level)
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{
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RT_ASSERT(0);
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}
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}
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/*@}*/
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