661 lines
18 KiB
C
661 lines
18 KiB
C
#include <rthw.h>
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#include <rtthread.h>
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#include <netif/ethernetif.h>
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#include "sam7x_emac.h"
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#include "AT91SAM7X256.h"
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#include "lwipopts.h"
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#include "lwip/mem.h"
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#define MAX_ADDR_LEN 6
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#ifdef DM9161
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#define EMAC_PIO_CFG (AT91C_PB8_EMDC | \
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AT91C_PB9_EMDIO | \
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AT91C_PB2_ETX0 | \
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AT91C_PB3_ETX1 | \
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AT91C_PB10_ETX2 | \
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AT91C_PB11_ETX3 | \
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AT91C_PB1_ETXEN | \
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AT91C_PB0_ETXCK_EREFCK | \
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AT91C_PB15_ERXDV_ECRSDV | \
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AT91C_PB5_ERX0 | \
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AT91C_PB6_ERX1 | \
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AT91C_PB12_ETXER | \
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AT91C_PB13_ERX2 | \
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AT91C_PB14_ERX3 | \
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AT91C_PB17_ERXCK | \
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AT91C_PB16_ECOL | \
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AT91C_PB4_ECRS | \
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AT91C_PB7_ERXER)
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#else
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#define EMAC_PIO_CFG (AT91C_PB0_ETXCK_EREFCK | \
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AT91C_PB1_ETXEN | \
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AT91C_PB2_ETX0 | \
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AT91C_PB3_ETX1 | \
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AT91C_PB4_ECRS | \
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AT91C_PB5_ERX0 | \
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AT91C_PB6_ERX1 | \
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AT91C_PB7_ERXER | \
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AT91C_PB8_EMDC | \
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AT91C_PB9_EMDIO | \
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AT91C_PB10_ETX2 | \
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AT91C_PB11_ETX3 | \
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AT91C_PB10_ETX2 | \
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AT91C_PB13_ERX2 | \
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AT91C_PB14_ERX3 | \
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AT91C_PB15_ERXDV_ECRSDV| \
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AT91C_PB16_ECOL | \
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AT91C_PB17_ERXCK)
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#endif
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#define RB_BUFFER_SIZE 8 /* max number of receive buffers */
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#define ETH_RX_BUF_SIZE 128
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#define TB_BUFFER_SIZE 4
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#define ETH_TX_BUF_SIZE (PBUF_POOL_BUFSIZE)
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struct rbf_t
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{
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rt_uint32_t addr;
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rt_uint32_t status;
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};
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static rt_uint32_t current_rb_index; /* current receive buffer index */
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static volatile struct rbf_t rb_descriptors[RB_BUFFER_SIZE];
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static volatile struct rbf_t tb_descriptors[TB_BUFFER_SIZE];
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static rt_uint8_t rx_buf[RB_BUFFER_SIZE][ETH_RX_BUF_SIZE] __attribute__ ((aligned (8)));
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static rt_uint8_t tx_buf[TB_BUFFER_SIZE][ETH_TX_BUF_SIZE] __attribute__ ((aligned (8)));
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static struct rt_semaphore tx_sem;
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struct net_device
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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/* interface address info. */
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rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
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};
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static struct net_device sam7x_dev_entry;
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static struct net_device *sam7x_dev =&sam7x_dev_entry;
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AT91PS_EMAC pEmac = AT91C_BASE_EMAC;
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rt_inline void write_phy(rt_uint8_t addr, rt_uint32_t value)
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{
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AT91C_BASE_EMAC->EMAC_MAN = ((0x01<<30) | (2 << 16) | (1 << 28) |
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(AT91C_PHY_ADDR << 23) | (addr << 18)) | value;
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/* Wait until IDLE bit in Network Status register is cleared */
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while (!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE));
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}
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rt_inline rt_uint32_t read_phy(rt_uint8_t addr)
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{
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AT91C_BASE_EMAC->EMAC_MAN = (0x01<<30) | (0x02 << 16) | (0x02 << 28) |
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(AT91C_PHY_ADDR << 23) | (addr << 18);
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/* Wait until IDLE bit in Network Status register is cleared */
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while (!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE));
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return (AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff);
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}
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rt_inline void sam7xether_reset_tx_desc(void)
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{
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static rt_uint32_t index = 0;
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if(tb_descriptors[index].status & TxDESC_STATUS_USED)
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{
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while(!(tb_descriptors[index].status & TxDESC_STATUS_LAST_BUF))
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{
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index ++;
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if(index >= TB_BUFFER_SIZE)index = 0;
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tb_descriptors[index].status |= TxDESC_STATUS_USED;
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}
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index ++;
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if(index >= TB_BUFFER_SIZE)index = 0;
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}
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}
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/* interrupt service routing */
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static void sam7xether_isr(int irq, void* param)
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{
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/* Variable definitions can be made now. */
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volatile rt_uint32_t isr, rsr;
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/* get status */
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isr = AT91C_BASE_EMAC->EMAC_ISR;
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rsr = AT91C_BASE_EMAC->EMAC_RSR;
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if( ( isr & AT91C_EMAC_RCOMP ) || ( rsr & AT91C_EMAC_REC ) )
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{
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rt_err_t result;
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/* a frame has been received */
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result = eth_device_ready((struct eth_device*)&(sam7x_dev->parent));
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RT_ASSERT(result == RT_EOK);
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AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC;
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}
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if( isr & AT91C_EMAC_TCOMP )
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{
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/* A frame has been transmitted. Mark all the buffers as free */
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sam7xether_reset_tx_desc();
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AT91C_BASE_EMAC->EMAC_TSR = AT91C_EMAC_COMP;
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}
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}
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rt_inline void linksetup(void)
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{
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rt_uint32_t value, tout, id1, id2;
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#ifdef DM9161
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rt_uint32_t ulBMSR,ulBMCR,i;
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#endif
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#ifdef DM9161
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//PHY has internal pull down : disable MII isolate
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tout = read_phy(PHY_REG_BMCR);
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tout = read_phy(PHY_REG_BMCR);
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tout &= ~BMCR_ISOLATE;
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write_phy(PHY_REG_BMCR, tout);
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/* Check if this is a RTL8201 or DM9161 PHY. */
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id1 = read_phy(PHY_REG_PHYID1);
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id2 = read_phy(PHY_REG_PHYID2);
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if (((id1 << 16) | (id2 & 0xfff0)) == MII_DM9161_ID)
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{
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rt_kprintf("read MII_DM9161_ID ok!\n");
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tout = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
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DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
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write_phy(PHY_REG_ANAR, tout);
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// Wait for PHY auto negotiation completed
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i = 0;
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do {
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ulBMSR = read_phy(PHY_REG_BMSR);
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ulBMSR = read_phy(PHY_REG_BMSR);
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i++;
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if(i >= 0xffff)
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break;
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}while (!(ulBMSR & BMSR_ANEGCOMPLETE));
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if(i >= 0xffff)
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rt_kprintf("PHY No Link!\n");
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else
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rt_kprintf("PHY auto negotiation completed!\n");
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/* Update the MAC register NCFGR. */
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AT91C_BASE_EMAC->EMAC_NCFGR = 0;
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ulBMCR = read_phy(PHY_REG_BMCR);
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if (ulBMCR & BMCR_ANENABLE)
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{
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/* AutoNegotiation is enabled. */
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if(!(ulBMSR & BMSR_ANEGCOMPLETE))
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{
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/* Auto-negotitation in progress. */
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rt_kprintf("Auto-negotitation in progress!\n");
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return;
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}
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if (ulBMCR & BMCR_SPEED100)
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{
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/* Speed 100Mbit is enabled. */
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AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_SPD;
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}
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if (ulBMCR & BMCR_FULLDPLX)
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{
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/* Full duplex is enabled. */
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AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_FD;
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}
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}
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}
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#else
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/* Check if this is a RTL8201 or DM9161 PHY. */
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id1 = read_phy(PHY_REG_PHYID1);
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id2 = read_phy(PHY_REG_PHYID2);
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if (((id2 << 16) | (id1 & 0xfff0)) == MII_RTL8201_ID)
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{
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rt_kprintf("read MII_RTL8201_ID ok!\n");
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/* Configure the PHY device */
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/* Use autonegotiation about the link speed. */
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write_phy (PHY_REG_BMCR, PHY_AUTO_NEG);
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/* Wait to complete Auto_Negotiation. */
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for (tout = 0; tout < 0x100000; tout++)
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{
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value = read_phy (PHY_REG_BMSR);
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if (value & BMSR_ANEGCOMPLETE) break; /* autonegotiation finished. */
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}
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/* Check the link status. */
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for (tout = 0; tout < 0x10000; tout++)
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{
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value = read_phy (PHY_REG_BMSR);
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if (value & BMSR_LINKST) break; /* Link is on. */
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}
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}
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value = read_phy (PHY_REG_ANLPAR);
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/* Update the MAC register NCFGR. */
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AT91C_BASE_EMAC->EMAC_NCFGR &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
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/* set full duplex . */
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if (value & 0xA000) AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_FD;
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/* set speed */
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if (value & 0xC000) AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_SPD;
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#endif
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}
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/*
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* Set the MAC address.
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*/
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rt_inline void update_mac_address(struct net_device* device)
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{
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AT91C_BASE_EMAC->EMAC_SA1L = (device->dev_addr[3] << 24) |
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(device->dev_addr[2] << 16) |
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(device->dev_addr[1] << 8) |
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device->dev_addr[0];
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AT91C_BASE_EMAC->EMAC_SA1H = (device->dev_addr[5] << 8) |
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device->dev_addr[4];
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}
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rt_inline void sam7xether_desc_init()
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{
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rt_uint32_t i;
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/* Rx Buffer Descriptor initialization */
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current_rb_index = 0;
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for (i = 0; i < RB_BUFFER_SIZE; i++)
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{
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rb_descriptors[i].addr = (rt_uint32_t)&(rx_buf[i][0]);
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rb_descriptors[i].status = 0;
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}
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/* Set the WRAP bit at the end of the list descriptor. */
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rb_descriptors[RB_BUFFER_SIZE-1].addr |= 0x02;
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/* Set Rx Queue pointer to descriptor list. */
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AT91C_BASE_EMAC->EMAC_RBQP = (unsigned int)&(rb_descriptors[0]);
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/* Tx Buffer Descriptor initialization */
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for (i = 0; i < TB_BUFFER_SIZE; i++)
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{
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tb_descriptors[i].addr = (rt_uint32_t)&(tx_buf[i][0]);
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tb_descriptors[i].status = TxDESC_STATUS_USED;
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}
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/* Set the WRAP bit at the end of the list descriptor. */
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tb_descriptors[TB_BUFFER_SIZE-1].status |= TxDESC_STATUS_WRAP;
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/* Set Tx Queue pointer to descriptor list. */
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AT91C_BASE_EMAC->EMAC_TBQP = (unsigned int)&(tb_descriptors[0]);
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}
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/* RT-Thread Device Interface */
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/* initialize the interface */
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rt_err_t sam7xether_init(rt_device_t dev)
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{
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rt_uint32_t i;
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/* enable peripheral clock for EMAC and PIO B */
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB | 1 << AT91C_ID_EMAC;
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/* Disable pull up on RXDV => PHY normal mode (not in test mode), */
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/* and set MII mode. PHY has internal pull down. */
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AT91C_BASE_PIOB->PIO_PPUDR = (1<<16) | (1 << 15);
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/* Clear PB18 <=> PHY powerdown */
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AT91C_BASE_PIOB->PIO_PER = 1<<18;
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AT91C_BASE_PIOB->PIO_OER = 1<<18;
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AT91C_BASE_PIOB->PIO_CODR = 1<<18;
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/* EMAC IO init for EMAC-PHY communication. */
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AT91C_BASE_PIOB->PIO_ASR = EMAC_PIO_CFG;
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AT91C_BASE_PIOB->PIO_PDR = EMAC_PIO_CFG; // Set in Periph mode
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/* Enable communication between EMAC-PHY. */
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AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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/* MDC = MCK/32 */
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AT91C_BASE_EMAC->EMAC_NCFGR |= 2<<10;
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/* Reset PHY */
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AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB7_ERXER;
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AT91C_BASE_RSTC->RSTC_RMR = 0xA5000000 | (0x08 << 8) ;
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AT91C_BASE_RSTC->RSTC_RCR = 0xA5000000 | AT91C_RSTC_EXTRST;
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i = 0;
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while(!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL))
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{
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i++;
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if(i >= 0xfffff)
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break;
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}
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for(i=0; i<0xfffff; i++);//* <20>ȴ<EFBFBD>һ<EFBFBD><D2BB>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>ʱ<EFBFBD>䣬ʹPHY<48><59><EFBFBD><EFBFBD>
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linksetup();
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rt_kprintf("linksetup ok!\n");
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/* Disable management port in MAC control register. */
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AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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/* Enable EMAC in MII mode, enable clock ERXCK and ETXCK */
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AT91C_BASE_EMAC->EMAC_USRIO= AT91C_EMAC_CLKEN;
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/* Transmit and Receive disable. */
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AT91C_BASE_EMAC->EMAC_NCR &= ~(AT91C_EMAC_RE | AT91C_EMAC_TE);
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/* init descriptor */
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sam7xether_desc_init();
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/* Clear receive and transmit status registers. */
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AT91C_BASE_EMAC->EMAC_RSR = (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
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AT91C_BASE_EMAC->EMAC_TSR = (AT91C_EMAC_UND | AT91C_EMAC_COMP| AT91C_EMAC_BEX |
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AT91C_EMAC_RLES| AT91C_EMAC_COL | AT91C_EMAC_UBR);
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/* Configure EMAC operation mode. */
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//AT91C_BASE_EMAC->EMAC_NCFGR |= (AT91C_EMAC_BIG | AT91C_EMAC_DRFCS);
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч֡<D0A7><D6A1><EFBFBD><EFBFBD><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD> *<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>FCS<43>ֶ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>չ㲥֡ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1526<32>ֽڳ<D6BD>֡
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AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_CAF |AT91C_EMAC_DRFCS | AT91C_EMAC_NBC | AT91C_EMAC_BIG;
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AT91C_BASE_EMAC->EMAC_NCR |= (AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT);
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/* update MAC address */
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update_mac_address(sam7x_dev);
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/* enable interrupt */
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AT91C_BASE_EMAC->EMAC_IDR = 0x3fff;
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AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
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/* setup interrupt */
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rt_hw_interrupt_install(AT91C_ID_EMAC, sam7xether_isr, RT_NULL, "emac");
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*(volatile unsigned int*)(0xFFFFF000 + AT91C_ID_EMAC * 4) = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | 5;
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// AT91C_AIC_SMR(AT91C_ID_EMAC) = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | 5;
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rt_hw_interrupt_umask(AT91C_ID_EMAC);
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return RT_EOK;
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}
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/* control the interface */
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rt_err_t sam7xether_control(rt_device_t dev, rt_uint8_t cmd, void *args)
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{
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switch(cmd)
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{
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case NIOCTL_GADDR:
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/* get mac address */
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if(args) rt_memcpy(args, sam7x_dev_entry.dev_addr, 6);
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else return -RT_ERROR;
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break;
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default :
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break;
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}
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return RT_EOK;
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}
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/* Open the ethernet interface */
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rt_err_t sam7xether_open(rt_device_t dev, rt_uint16_t oflags)
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{
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return RT_EOK;
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}
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/* Close the interface */
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rt_err_t sam7xether_close(rt_device_t dev)
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{
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return RT_EOK;
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}
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/* Read */
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rt_size_t sam7xether_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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{
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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/* Write */
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rt_size_t sam7xether_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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{
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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/* See the header file for descriptions of public functions. */
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void sam7xether_write_frame(rt_uint8_t *ptr, rt_uint32_t length, rt_bool_t eof)
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{
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rt_uint8_t *buf_ptr;
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static rt_uint32_t current_tb_index = 0;
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rt_uint32_t is_last, tx_offset = 0, remain, pdu_length;
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while(tx_offset < length)
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{
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/* check whether buffer is available */
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while(!(tb_descriptors[current_tb_index].status & TxDESC_STATUS_USED))
|
||
{
|
||
/* no buffer */
|
||
rt_thread_delay(5);
|
||
}
|
||
|
||
/* Get the address of the buffer from the descriptor, then copy
|
||
the data into the buffer. */
|
||
buf_ptr = (rt_uint8_t *)tb_descriptors[current_tb_index].addr;
|
||
|
||
/* How much can we write to the buffer? */
|
||
remain = length - tx_offset;
|
||
pdu_length = (remain <= ETH_TX_BUF_SIZE)? remain : ETH_TX_BUF_SIZE;
|
||
|
||
/* Copy the data into the buffer. */
|
||
rt_memcpy(buf_ptr, &ptr[tx_offset], pdu_length );
|
||
tx_offset += pdu_length;
|
||
|
||
/* Is this the last data for the frame? */
|
||
if((eof == RT_TRUE) && ( tx_offset >= length )) is_last = TxDESC_STATUS_LAST_BUF;
|
||
else is_last = 0;
|
||
|
||
/* Fill out the necessary in the descriptor to get the data sent,
|
||
then move to the next descriptor, wrapping if necessary. */
|
||
if(current_tb_index >= (TB_BUFFER_SIZE - 1))
|
||
{
|
||
tb_descriptors[current_tb_index].status = ( pdu_length & TxDESC_STATUS_BUF_SIZE )
|
||
| is_last
|
||
| TxDESC_STATUS_WRAP;
|
||
current_tb_index = 0;
|
||
}
|
||
else
|
||
{
|
||
tb_descriptors[current_tb_index].status = ( pdu_length & TxDESC_STATUS_BUF_SIZE )
|
||
| is_last;
|
||
current_tb_index++;
|
||
}
|
||
|
||
/* If this is the last buffer to be sent for this frame we can
|
||
start the transmission. */
|
||
if(is_last)
|
||
{
|
||
AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
|
||
}
|
||
}
|
||
}
|
||
|
||
/* ethernet device interface */
|
||
/*
|
||
* Transmit packet.
|
||
*/
|
||
rt_err_t sam7xether_tx( rt_device_t dev, struct pbuf* p)
|
||
{
|
||
struct pbuf* q;
|
||
|
||
/* lock tx operation */
|
||
rt_sem_take(&tx_sem, RT_WAITING_FOREVER);
|
||
|
||
for (q = p; q != NULL; q = q->next)
|
||
{
|
||
if (q->next == RT_NULL) sam7xether_write_frame(q->payload, q->len, RT_TRUE);
|
||
else sam7xether_write_frame(q->payload, q->len, RT_FALSE);
|
||
}
|
||
|
||
rt_sem_release(&tx_sem);
|
||
|
||
return 0;
|
||
}
|
||
|
||
void sam7xether_read_frame(rt_uint8_t* ptr, rt_uint32_t section_length, rt_uint32_t total)
|
||
{
|
||
static rt_uint8_t* src_ptr;
|
||
register rt_uint32_t buf_remain, section_remain;
|
||
static rt_uint32_t section_read = 0, buf_offset = 0, frame_read = 0;
|
||
|
||
if(ptr == RT_NULL)
|
||
{
|
||
/* Reset our state variables ready for the next read from this buffer. */
|
||
src_ptr = (rt_uint8_t *)(rb_descriptors[current_rb_index].addr & RxDESC_FLAG_ADDR_MASK);
|
||
frame_read = (rt_uint32_t)0;
|
||
buf_offset = (rt_uint32_t)0;
|
||
}
|
||
else
|
||
{
|
||
/* Loop until we have obtained the required amount of data. */
|
||
section_read = 0;
|
||
while( section_read < section_length )
|
||
{
|
||
buf_remain = (ETH_RX_BUF_SIZE - buf_offset);
|
||
section_remain = section_length - section_read;
|
||
|
||
if( section_remain > buf_remain )
|
||
{
|
||
/* more data on section than buffer size */
|
||
rt_memcpy(&ptr[ section_read ], &src_ptr[buf_offset], buf_remain);
|
||
section_read += buf_remain;
|
||
frame_read += buf_remain;
|
||
|
||
/* free buffer */
|
||
rb_descriptors[current_rb_index].addr &= ~RxDESC_FLAG_OWNSHIP;
|
||
|
||
/* move to the next frame. */
|
||
current_rb_index++;
|
||
if(current_rb_index >= RB_BUFFER_SIZE) current_rb_index = 0;
|
||
|
||
/* Reset the variables for the new buffer. */
|
||
src_ptr = (rt_uint8_t *)(rb_descriptors[current_rb_index].addr & RxDESC_FLAG_ADDR_MASK);
|
||
buf_offset = 0;
|
||
}
|
||
else
|
||
{
|
||
/* more data on buffer than section size */
|
||
rt_memcpy(&ptr[section_read], &src_ptr[buf_offset], section_remain);
|
||
buf_offset += section_remain;
|
||
section_read += section_remain;
|
||
frame_read += section_remain;
|
||
|
||
/* finish this read */
|
||
if((buf_offset >= ETH_RX_BUF_SIZE) || (frame_read >= total))
|
||
{
|
||
/* free buffer */
|
||
rb_descriptors[current_rb_index].addr &= ~(RxDESC_FLAG_OWNSHIP);
|
||
|
||
/* move to the next frame. */
|
||
current_rb_index++;
|
||
if( current_rb_index >= RB_BUFFER_SIZE ) current_rb_index = 0;
|
||
|
||
src_ptr = (rt_uint8_t*)(rb_descriptors[current_rb_index].addr & RxDESC_FLAG_ADDR_MASK);
|
||
buf_offset = 0;
|
||
}
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
struct pbuf *sam7xether_rx(rt_device_t dev)
|
||
{
|
||
struct pbuf *p = RT_NULL;
|
||
|
||
/* skip fragment frame */
|
||
while((rb_descriptors[current_rb_index].addr & RxDESC_FLAG_OWNSHIP)
|
||
&& !(rb_descriptors[current_rb_index].status & RxDESC_STATUS_FRAME_START))
|
||
{
|
||
rb_descriptors[current_rb_index].addr &= (~RxDESC_FLAG_OWNSHIP);
|
||
|
||
current_rb_index++;
|
||
if(current_rb_index >= RB_BUFFER_SIZE) current_rb_index = 0;
|
||
}
|
||
|
||
if ((rb_descriptors[current_rb_index].addr & RxDESC_FLAG_OWNSHIP))
|
||
{
|
||
struct pbuf* q;
|
||
rt_uint32_t index, pkt_len = 0;
|
||
|
||
/* first of all, find the frame length */
|
||
index = current_rb_index;
|
||
while (rb_descriptors[index].addr & RxDESC_FLAG_OWNSHIP)
|
||
{
|
||
pkt_len = rb_descriptors[index].status & RxDESC_STATUS_BUF_SIZE;
|
||
if (pkt_len > 0) break;
|
||
|
||
index ++;
|
||
if (index >= RB_BUFFER_SIZE) index = 0;
|
||
}
|
||
|
||
if (pkt_len)
|
||
{
|
||
//p = pbuf_alloc(PBUF_LINK, pkt_len, PBUF_RAM);
|
||
p = pbuf_alloc(PBUF_RAW, pkt_len, PBUF_POOL);
|
||
if(p != RT_NULL)
|
||
{
|
||
sam7xether_read_frame(RT_NULL, 0, pkt_len);
|
||
for(q = p; q != RT_NULL; q= q->next)
|
||
sam7xether_read_frame(q->payload, q->len, pkt_len);
|
||
}
|
||
else
|
||
{
|
||
rt_kprintf("no memory in pbuf\n");
|
||
}
|
||
}
|
||
}
|
||
|
||
/* enable interrupt */
|
||
AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
|
||
|
||
return p;
|
||
}
|
||
|
||
int sam7xether_register(char *name)
|
||
{
|
||
rt_err_t result;
|
||
|
||
/* init rt-thread device interface */
|
||
sam7x_dev_entry.parent.parent.init = sam7xether_init;
|
||
sam7x_dev_entry.parent.parent.open = sam7xether_open;
|
||
sam7x_dev_entry.parent.parent.close = sam7xether_close;
|
||
sam7x_dev_entry.parent.parent.read = sam7xether_read;
|
||
sam7x_dev_entry.parent.parent.write = sam7xether_write;
|
||
sam7x_dev_entry.parent.parent.control = sam7xether_control;
|
||
sam7x_dev_entry.parent.eth_rx = sam7xether_rx;
|
||
sam7x_dev_entry.parent.eth_tx = sam7xether_tx;
|
||
|
||
/* Update MAC address */
|
||
sam7x_dev_entry.dev_addr[0] = 0x1e;
|
||
sam7x_dev_entry.dev_addr[1] = 0x30;
|
||
sam7x_dev_entry.dev_addr[2] = 0x6c;
|
||
sam7x_dev_entry.dev_addr[3] = 0xa2;
|
||
sam7x_dev_entry.dev_addr[4] = 0x45;
|
||
sam7x_dev_entry.dev_addr[5] = 0x5e;
|
||
/* update mac address */
|
||
update_mac_address(sam7x_dev);
|
||
|
||
rt_sem_init(&tx_sem, "emac", 1, RT_IPC_FLAG_FIFO);
|
||
|
||
result = eth_device_init(&(sam7x_dev->parent), (char*)name);
|
||
RT_ASSERT(result == RT_EOK);
|
||
|
||
return RT_EOK;
|
||
}
|