485 lines
11 KiB
C
485 lines
11 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-03-04 stevetong459 first version
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*/
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#include <board.h>
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#ifdef RT_USING_PWM
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#include <drivers/rt_drv_pwm.h>
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#define LOG_TAG "drv.pwm"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#define MAX_PERIOD 65535
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#define MIN_PERIOD 3
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#define MIN_PULSE 2
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#define _PWM_GPIO_INIT(port_num, pin_num) \
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do \
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{ \
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIO##port_num); \
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gpio_config->pin = GPIO_PIN_##pin_num; \
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gpio_config->mode = GPIO_MODE_AF_PP; \
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gpio_config->speed = GPIO_SPEED_50MHz; \
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GPIO_Config(GPIO##port_num, gpio_config); \
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} while (0)
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enum
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{
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#ifdef BSP_USING_PWM1
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PWM1_INDEX,
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#endif
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#ifdef BSP_USING_PWM2
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PWM2_INDEX,
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#endif
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#ifdef BSP_USING_PWM3
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PWM3_INDEX,
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#endif
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#ifdef BSP_USING_PWM4
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PWM4_INDEX,
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#endif
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#ifdef BSP_USING_PWM5
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PWM5_INDEX,
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#endif
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#ifdef BSP_USING_PWM8
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PWM8_INDEX,
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#endif
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};
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struct apm32_pwm
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{
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char *name;
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TMR_T *tmr;
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rt_uint8_t channel;
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struct rt_device_pwm pwm_device;
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};
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static struct apm32_pwm pwm_config[] =
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{
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#ifdef BSP_USING_PWM1
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{
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"pwm1",
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TMR1,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM2
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{
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"pwm2",
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TMR2,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM3
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{
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"pwm3",
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TMR3,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM4
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{
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"pwm4",
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TMR4,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM5
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{
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"pwm5",
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TMR5,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM8
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{
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"pwm8",
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TMR8,
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0,
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},
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#endif
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};
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static void _pwm_channel_init(GPIO_Config_T *gpio_config)
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{
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#ifdef BSP_USING_PWM1_CH1
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pwm_config[PWM1_INDEX].channel |= 1 << 0;
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_PWM_GPIO_INIT(A, 8);
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#endif
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#ifdef BSP_USING_PWM1_CH2
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pwm_config[PWM1_INDEX].channel |= 1 << 1;
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_PWM_GPIO_INIT(A, 9);
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#endif
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#ifdef BSP_USING_PWM1_CH3
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pwm_config[PWM1_INDEX].channel |= 1 << 2;
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_PWM_GPIO_INIT(A, 10);
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#endif
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#ifdef BSP_USING_PWM1_CH4
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pwm_config[PWM1_INDEX].channel |= 1 << 3;
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_PWM_GPIO_INIT(A, 11);
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#endif
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#ifdef BSP_USING_PWM2_CH1
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pwm_config[PWM2_INDEX].channel |= 1 << 0;
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_PWM_GPIO_INIT(A, 0);
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#endif
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#ifdef BSP_USING_PWM2_CH2
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pwm_config[PWM2_INDEX].channel |= 1 << 1;
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_PWM_GPIO_INIT(A, 1);
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#endif
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#ifdef BSP_USING_PWM2_CH3
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pwm_config[PWM2_INDEX].channel |= 1 << 2;
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_PWM_GPIO_INIT(A, 2);
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#endif
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#ifdef BSP_USING_PWM2_CH4
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pwm_config[PWM2_INDEX].channel |= 1 << 3;
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_PWM_GPIO_INIT(A, 3);
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#endif
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#ifdef BSP_USING_PWM3_CH1
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pwm_config[PWM3_INDEX].channel |= 1 << 0;
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GPIO_ConfigPinRemap(GPIO_FULL_REMAP_TMR3);
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_PWM_GPIO_INIT(C, 6);
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#endif
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#ifdef BSP_USING_PWM3_CH2
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pwm_config[PWM3_INDEX].channel |= 1 << 1;
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GPIO_ConfigPinRemap(GPIO_FULL_REMAP_TMR3);
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_PWM_GPIO_INIT(C, 7);
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#endif
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#ifdef BSP_USING_PWM3_CH3
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pwm_config[PWM3_INDEX].channel |= 1 << 2;
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GPIO_ConfigPinRemap(GPIO_FULL_REMAP_TMR3);
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_PWM_GPIO_INIT(C, 8);
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#endif
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#ifdef BSP_USING_PWM3_CH4
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pwm_config[PWM3_INDEX].channel |= 1 << 3;
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GPIO_ConfigPinRemap(GPIO_FULL_REMAP_TMR3);
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_PWM_GPIO_INIT(C, 9);
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#endif
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#ifdef BSP_USING_PWM4_CH1
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pwm_config[PWM4_INDEX].channel |= 1 << 0;
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_PWM_GPIO_INIT(B, 6);
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#endif
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#ifdef BSP_USING_PWM4_CH2
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pwm_config[PWM4_INDEX].channel |= 1 << 1;
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_PWM_GPIO_INIT(B, 7);
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#endif
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#ifdef BSP_USING_PWM4_CH3
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pwm_config[PWM4_INDEX].channel |= 1 << 2;
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_PWM_GPIO_INIT(B, 8);
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#endif
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#ifdef BSP_USING_PWM4_CH4
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pwm_config[PWM4_INDEX].channel |= 1 << 3;
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_PWM_GPIO_INIT(B, 9);
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#endif
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#ifdef BSP_USING_PWM5_CH1
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pwm_config[PWM5_INDEX].channel |= 1 << 0;
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_PWM_GPIO_INIT(A, 0);
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#endif
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#ifdef BSP_USING_PWM5_CH2
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pwm_config[PWM5_INDEX].channel |= 1 << 1;
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_PWM_GPIO_INIT(A, 1);
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#endif
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#ifdef BSP_USING_PWM5_CH3
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pwm_config[PWM5_INDEX].channel |= 1 << 2;
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_PWM_GPIO_INIT(A, 2);
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#endif
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#ifdef BSP_USING_PWM5_CH4
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pwm_config[PWM5_INDEX].channel |= 1 << 3;
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_PWM_GPIO_INIT(A, 3);
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#endif
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#ifdef BSP_USING_PWM8_CH1
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pwm_config[PWM8_INDEX].channel |= 1 << 0;
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_PWM_GPIO_INIT(C, 6);
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#endif
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#ifdef BSP_USING_PWM8_CH2
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pwm_config[PWM8_INDEX].channel |= 1 << 1;
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_PWM_GPIO_INIT(C, 7);
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#endif
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#ifdef BSP_USING_PWM8_CH3
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pwm_config[PWM8_INDEX].channel |= 1 << 2;
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_PWM_GPIO_INIT(C, 8);
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#endif
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#ifdef BSP_USING_PWM8_CH4
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pwm_config[PWM8_INDEX].channel |= 1 << 3;
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_PWM_GPIO_INIT(C, 9);
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#endif
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}
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static rt_err_t _pwm_hw_init(struct apm32_pwm *device)
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{
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rt_err_t result = RT_EOK;
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TMR_T *tmr = RT_NULL;
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TMR_BaseConfig_T base_config;
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TMR_OCConfig_T oc_config;
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RT_ASSERT(device != RT_NULL);
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tmr = (TMR_T *)device->tmr;
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if (tmr == TMR1)
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{
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR1);
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}
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else if (tmr == TMR8)
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{
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR8);
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}
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else if (tmr == TMR2)
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{
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RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR2);
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}
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else if (tmr == TMR3)
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{
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RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR3);
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}
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else if (tmr == TMR4)
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{
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RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR4);
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}
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else if (tmr == TMR5)
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{
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RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR5);
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}
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/* configure the tmrer to pwm mode */
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base_config.division = 0;
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base_config.countMode = TMR_COUNTER_MODE_UP;
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base_config.period = 0;
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base_config.clockDivision = TMR_CLOCK_DIV_1;
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TMR_ConfigTimeBase(tmr, &base_config);
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TMR_SelectOutputTrigger(tmr, TMR_TRGO_SOURCE_RESET);
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TMR_DisableMasterSlaveMode(tmr);
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oc_config.mode = TMR_OC_MODE_PWM1;
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oc_config.pulse = 0;
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oc_config.polarity = TMR_OC_POLARITY_HIGH;
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oc_config.nIdleState = TMR_OC_NIDLE_STATE_RESET;
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oc_config.idleState = TMR_OC_IDLE_STATE_RESET;
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oc_config.outputState = TMR_OC_STATE_ENABLE;
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/* config pwm channel */
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if (device->channel & 0x01)
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{
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TMR_ConfigOC1(tmr, &oc_config);
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}
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if (device->channel & 0x02)
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{
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TMR_ConfigOC2(tmr, &oc_config);
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}
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if (device->channel & 0x04)
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{
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TMR_ConfigOC3(tmr, &oc_config);
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}
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if (device->channel & 0x08)
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{
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TMR_ConfigOC4(tmr, &oc_config);
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}
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/* enable update request source */
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TMR_ConfigUpdateRequest(tmr, TMR_UPDATE_SOURCE_REGULAR);
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return result;
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}
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static rt_uint32_t _pwm_timer_clock_get(TMR_T *tmr)
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{
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uint32_t pclk1;
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RCM_ReadPCLKFreq(&pclk1, NULL);
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return (rt_uint32_t)(pclk1 * ((RCM->CFG_B.APB1PSC != RCM_APB_DIV_1) ? 2 : 1));
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}
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static rt_err_t _pwm_enable(TMR_T *tmr, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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{
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rt_uint32_t channel = (configuration->channel - 1) << 2;
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if (enable)
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{
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if (configuration->complementary)
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{
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TMR_EnableCCxNChannel(tmr, (TMR_CHANNEL_T)(0x01 << (channel & 0x1FU)));
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}
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else
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{
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TMR_EnableCCxChannel(tmr, (TMR_CHANNEL_T)(0x01 << (channel & 0x1FU)));
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}
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if (tmr == TMR1 || tmr == TMR8)
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{
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TMR_EnablePWMOutputs(tmr);
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}
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TMR_Enable(tmr);
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}
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else
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{
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if (configuration->complementary)
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{
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TMR_DisableCCxNChannel(tmr, (TMR_CHANNEL_T)(0x01 << (channel & 0x1FU)));
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}
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else
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{
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TMR_DisableCCxChannel(tmr, (TMR_CHANNEL_T)(0x01 << (channel & 0x1FU)));
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}
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if (tmr == TMR1 || tmr == TMR8)
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{
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TMR_DisablePWMOutputs(tmr);
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}
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TMR_Disable(tmr);
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}
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return RT_EOK;
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}
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static rt_err_t _pwm_get(TMR_T *tmr, struct rt_pwm_configuration *configuration)
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{
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/* Converts the channel number to the channel number of library */
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rt_uint32_t channel = (configuration->channel - 1) << 2;
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rt_uint64_t timer_clock;
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rt_uint32_t timer_reload, timer_psc;
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timer_clock = _pwm_timer_clock_get(tmr);
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if (tmr->CTRL1_B.CLKDIV == TMR_CLOCK_DIV_2)
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{
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timer_clock <<= 1;
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}
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else if (tmr->CTRL1_B.CLKDIV == TMR_CLOCK_DIV_4)
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{
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timer_clock <<= 2;
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}
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uint32_t temp;
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temp = (uint32_t)tmr;
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temp += (uint32_t)(0x34 + channel);
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/* Convert nanosecond to frequency and duty cycle.*/
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timer_clock /= 1000000UL;
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timer_reload = tmr->AUTORLD;
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timer_psc = tmr->PSC;
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configuration->period = (timer_reload + 1) * (timer_psc + 1) * 1000UL / timer_clock;
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configuration->pulse = ((*(__IO uint32_t *)temp) + 1) * (timer_psc + 1) * 1000UL / timer_clock;
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return RT_EOK;
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}
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static rt_err_t _pwm_set(TMR_T *tmr, struct rt_pwm_configuration *configuration)
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{
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rt_uint32_t period, pulse;
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rt_uint64_t timer_clock, psc;
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rt_uint32_t channel = 0x04 * (configuration->channel - 1);
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uint32_t temp = (uint32_t)tmr;
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timer_clock = _pwm_timer_clock_get(tmr);
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/* Convert nanosecond to frequency and duty cycle. */
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timer_clock /= 1000000UL;
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period = (unsigned long long)configuration->period * timer_clock / 1000ULL ;
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psc = period / MAX_PERIOD + 1;
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period = period / psc;
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tmr->PSC = (uint16_t)(psc - 1);
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if (period < MIN_PERIOD)
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{
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period = MIN_PERIOD;
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}
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tmr->AUTORLD = (uint16_t)(period - 1);
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pulse = (unsigned long long)configuration->pulse * timer_clock / psc / 1000ULL;
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if (pulse < MIN_PULSE)
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{
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pulse = MIN_PULSE;
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}
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else if (pulse > period)
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{
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pulse = period;
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}
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temp += (uint32_t)(0x34 + channel);
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*(__IO uint32_t *)temp = pulse - 1;
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tmr->CNT = 0;
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/* Update frequency value */
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TMR_GenerateEvent(tmr, TMR_EVENT_UPDATE);
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return RT_EOK;
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}
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static rt_err_t _pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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TMR_T *tmr = (TMR_T *)device->parent.user_data;
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switch (cmd)
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{
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case PWMN_CMD_ENABLE:
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configuration->complementary = RT_TRUE;
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case PWM_CMD_ENABLE:
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return _pwm_enable(tmr, configuration, RT_TRUE);
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case PWMN_CMD_DISABLE:
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configuration->complementary = RT_FALSE;
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case PWM_CMD_DISABLE:
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return _pwm_enable(tmr, configuration, RT_FALSE);
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case PWM_CMD_SET:
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return _pwm_set(tmr, configuration);
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case PWM_CMD_GET:
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return _pwm_get(tmr, configuration);
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default:
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return RT_EINVAL;
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}
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}
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static const struct rt_pwm_ops _pwm_ops =
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{
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_pwm_control
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};
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static int rt_hw_pwm_init(void)
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{
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rt_uint32_t i = 0;
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rt_err_t result = RT_EOK;
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GPIO_Config_T gpio_config;
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_pwm_channel_init(&gpio_config);
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for (i = 0; i < sizeof(pwm_config) / sizeof(pwm_config[0]); i++)
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{
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/* pwm init */
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if (_pwm_hw_init(&pwm_config[i]) != RT_EOK)
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{
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LOG_E("%s init failed", pwm_config[i].name);
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return -RT_ERROR;
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}
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else
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{
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LOG_D("%s init success", pwm_config[i].name);
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/* register pwm device */
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if (rt_device_pwm_register(&pwm_config[i].pwm_device, pwm_config[i].name, &_pwm_ops, pwm_config[i].tmr) == RT_EOK)
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{
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LOG_D("%s register success", pwm_config[i].name);
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}
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else
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{
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LOG_E("%s register failed", pwm_config[i].name);
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result = -RT_ERROR;
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}
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}
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}
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return result;
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}
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INIT_DEVICE_EXPORT(rt_hw_pwm_init);
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#endif /* RT_USING_PWM */
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