90 lines
1.9 KiB
C
90 lines
1.9 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-04-02 tanek first implementation
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* 2019-04-27 misonyo update to cortex-m7 series
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*/
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#include <rthw.h>
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#include <rtdef.h>
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#include <board.h>
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/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */
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#define L1CACHE_LINESIZE_BYTE (32)
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void rt_hw_cpu_icache_enable(void)
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{
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SCB_EnableICache();
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}
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void rt_hw_cpu_icache_disable(void)
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{
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SCB_DisableICache();
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}
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rt_base_t rt_hw_cpu_icache_status(void)
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{
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return 0;
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}
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void rt_hw_cpu_icache_ops(int ops, void* addr, int size)
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{
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rt_uint32_t address = (rt_uint32_t)addr & (rt_uint32_t) ~(L1CACHE_LINESIZE_BYTE - 1);
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rt_int32_t size_byte = size + address - (rt_uint32_t)addr;
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rt_uint32_t linesize = 32U;
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if (ops & RT_HW_CACHE_INVALIDATE)
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{
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__DSB();
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while (size_byte > 0)
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{
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SCB->ICIMVAU = address;
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address += linesize;
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size_byte -= linesize;
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}
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__DSB();
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__ISB();
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}
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}
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void rt_hw_cpu_dcache_enable(void)
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{
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SCB_EnableDCache();
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}
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void rt_hw_cpu_dcache_disable(void)
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{
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SCB_DisableDCache();
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}
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rt_base_t rt_hw_cpu_dcache_status(void)
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{
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return 0;
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}
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void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
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{
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rt_uint32_t startAddr = (rt_uint32_t)addr & (rt_uint32_t)~(L1CACHE_LINESIZE_BYTE - 1);
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rt_uint32_t size_byte = size + (rt_uint32_t)addr - startAddr;
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if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE))
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{
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SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte);
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}
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else if (ops & RT_HW_CACHE_FLUSH)
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{
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SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size_byte);
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}
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else if (ops & RT_HW_CACHE_INVALIDATE)
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{
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SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte);
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}
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else
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{
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RT_ASSERT(0);
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}
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}
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