473 lines
22 KiB
C
473 lines
22 KiB
C
/*
|
|
* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without modification,
|
|
* are permitted provided that the following conditions are met:
|
|
*
|
|
* o Redistributions of source code must retain the above copyright notice, this list
|
|
* of conditions and the following disclaimer.
|
|
*
|
|
* o Redistributions in binary form must reproduce the above copyright notice, this
|
|
* list of conditions and the following disclaimer in the documentation and/or
|
|
* other materials provided with the distribution.
|
|
*
|
|
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
|
* contributors may be used to endorse or promote products derived from this
|
|
* software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
|
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
|
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
#ifndef _FSL_BITACCESS_H
|
|
#define _FSL_BITACCESS_H 1
|
|
|
|
#include <stdint.h>
|
|
#include <stdlib.h>
|
|
|
|
/* IO definitions (access restrictions to peripheral registers) */
|
|
#ifdef __cplusplus
|
|
#define __I volatile /*!< Defines 'read only' permissions */
|
|
#else
|
|
#define __I volatile const /*!< Defines 'read only' permissions */
|
|
#endif
|
|
#define __O volatile /*!< Defines 'write only' permissions */
|
|
#define __IO volatile /*!< Defines 'read / write' permissions */
|
|
|
|
/*
|
|
* Macros for single instance registers
|
|
*/
|
|
|
|
#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field)
|
|
#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field)
|
|
#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field)
|
|
|
|
#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v))
|
|
#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v))
|
|
#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v))
|
|
|
|
#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
|
|
#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym
|
|
|
|
#define BF_RD(reg, field) HW_##reg.B.field
|
|
#define BF_WR(reg, field, v) BW_##reg##_##field(v)
|
|
|
|
#define BF_CS1(reg, f1, v1) \
|
|
(HW_##reg##_CLR(BM_##reg##_##f1), \
|
|
HW_##reg##_SET(BF_##reg##_##f1(v1)))
|
|
|
|
#define BF_CS2(reg, f1, v1, f2, v2) \
|
|
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2), \
|
|
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2)))
|
|
|
|
#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \
|
|
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3), \
|
|
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3)))
|
|
|
|
#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
|
|
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4), \
|
|
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4)))
|
|
|
|
#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
|
|
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5), \
|
|
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5)))
|
|
|
|
#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
|
|
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5 | \
|
|
BM_##reg##_##f6), \
|
|
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5) | \
|
|
BF_##reg##_##f6(v6)))
|
|
|
|
#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
|
|
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5 | \
|
|
BM_##reg##_##f6 | \
|
|
BM_##reg##_##f7), \
|
|
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5) | \
|
|
BF_##reg##_##f6(v6) | \
|
|
BF_##reg##_##f7(v7)))
|
|
|
|
#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
|
|
(HW_##reg##_CLR(BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5 | \
|
|
BM_##reg##_##f6 | \
|
|
BM_##reg##_##f7 | \
|
|
BM_##reg##_##f8), \
|
|
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5) | \
|
|
BF_##reg##_##f6(v6) | \
|
|
BF_##reg##_##f7(v7) | \
|
|
BF_##reg##_##f8(v8)))
|
|
|
|
/*
|
|
* Macros for multiple instance registers
|
|
*/
|
|
|
|
#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field)
|
|
#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field)
|
|
#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field)
|
|
|
|
#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v))
|
|
#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v))
|
|
#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v))
|
|
|
|
#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
|
|
#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym
|
|
|
|
#define BF_RDn(reg, n, field) HW_##reg(n).B.field
|
|
#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v)
|
|
|
|
#define BF_CS1n(reg, n, f1, v1) \
|
|
(HW_##reg##_CLR(n, (BM_##reg##_##f1)), \
|
|
HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
|
|
|
|
#define BF_CS2n(reg, n, f1, v1, f2, v2) \
|
|
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2)), \
|
|
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2))))
|
|
|
|
#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \
|
|
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3)), \
|
|
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3))))
|
|
|
|
#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \
|
|
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4)), \
|
|
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4))))
|
|
|
|
#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
|
|
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5)), \
|
|
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5))))
|
|
|
|
#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
|
|
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5 | \
|
|
BM_##reg##_##f6)), \
|
|
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5) | \
|
|
BF_##reg##_##f6(v6))))
|
|
|
|
#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
|
|
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5 | \
|
|
BM_##reg##_##f6 | \
|
|
BM_##reg##_##f7)), \
|
|
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5) | \
|
|
BF_##reg##_##f6(v6) | \
|
|
BF_##reg##_##f7(v7))))
|
|
|
|
#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
|
|
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5 | \
|
|
BM_##reg##_##f6 | \
|
|
BM_##reg##_##f7 | \
|
|
BM_##reg##_##f8)), \
|
|
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5) | \
|
|
BF_##reg##_##f6(v6) | \
|
|
BF_##reg##_##f7(v7) | \
|
|
BF_##reg##_##f8(v8))))
|
|
|
|
/*
|
|
* Macros for single instance MULTI-BLOCK registers
|
|
*/
|
|
|
|
#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field)
|
|
#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field)
|
|
#define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field)
|
|
|
|
#define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v))
|
|
#define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v))
|
|
#define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v))
|
|
|
|
#define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
|
|
#define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym
|
|
|
|
#define BFn_RD(reg, blk, field) HW_##reg(blk).B.field
|
|
#define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v)
|
|
|
|
#define BFn_CS1(reg, blk, f1, v1) \
|
|
(HW_##reg##_CLR(blk, BM_##reg##_##f1), \
|
|
HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
|
|
|
|
#define BFn_CS2(reg, blk, f1, v1, f2, v2) \
|
|
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2), \
|
|
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2)))
|
|
|
|
#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \
|
|
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3), \
|
|
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3)))
|
|
|
|
#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \
|
|
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4), \
|
|
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4)))
|
|
|
|
#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
|
|
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5), \
|
|
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5)))
|
|
|
|
#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
|
|
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5 | \
|
|
BM_##reg##_##f6), \
|
|
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5) | \
|
|
BF_##reg##_##f6(v6)))
|
|
|
|
#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
|
|
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5 | \
|
|
BM_##reg##_##f6 | \
|
|
BM_##reg##_##f7), \
|
|
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5) | \
|
|
BF_##reg##_##f6(v6) | \
|
|
BF_##reg##_##f7(v7)))
|
|
|
|
#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
|
|
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5 | \
|
|
BM_##reg##_##f6 | \
|
|
BM_##reg##_##f7 | \
|
|
BM_##reg##_##f8), \
|
|
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5) | \
|
|
BF_##reg##_##f6(v6) | \
|
|
BF_##reg##_##f7(v7) | \
|
|
BF_##reg##_##f8(v8)))
|
|
|
|
/*
|
|
* Macros for MULTI-BLOCK multiple instance registers
|
|
*/
|
|
|
|
#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field)
|
|
#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field)
|
|
#define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field)
|
|
|
|
#define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
|
|
#define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
|
|
#define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
|
|
|
|
#define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
|
|
#define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym
|
|
|
|
#define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field
|
|
#define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v)
|
|
|
|
#define BFn_CS1n(reg, blk, n, f1, v1) \
|
|
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \
|
|
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
|
|
|
|
#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \
|
|
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2)), \
|
|
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2))))
|
|
|
|
#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \
|
|
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3)), \
|
|
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3))))
|
|
|
|
#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \
|
|
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4)), \
|
|
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4))))
|
|
|
|
#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
|
|
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5)), \
|
|
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5))))
|
|
|
|
#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
|
|
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5 | \
|
|
BM_##reg##_##f6)), \
|
|
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5) | \
|
|
BF_##reg##_##f6(v6))))
|
|
|
|
#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
|
|
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5 | \
|
|
BM_##reg##_##f6 | \
|
|
BM_##reg##_##f7)), \
|
|
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5) | \
|
|
BF_##reg##_##f6(v6) | \
|
|
BF_##reg##_##f7(v7))))
|
|
|
|
#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
|
|
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
|
|
BM_##reg##_##f2 | \
|
|
BM_##reg##_##f3 | \
|
|
BM_##reg##_##f4 | \
|
|
BM_##reg##_##f5 | \
|
|
BM_##reg##_##f6 | \
|
|
BM_##reg##_##f7 | \
|
|
BM_##reg##_##f8)), \
|
|
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
|
|
BF_##reg##_##f2(v2) | \
|
|
BF_##reg##_##f3(v3) | \
|
|
BF_##reg##_##f4(v4) | \
|
|
BF_##reg##_##f5(v5) | \
|
|
BF_##reg##_##f6(v6) | \
|
|
BF_##reg##_##f7(v7) | \
|
|
BF_##reg##_##f8(v8))))
|
|
|
|
#endif /* _FSL_BITACCESS_H */
|
|
|
|
/******************************************************************************/
|