139 lines
6.2 KiB
Plaintext
139 lines
6.2 KiB
Plaintext
/*
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** ###################################################################
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** Processors: LPC54114J256BD64_M4
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** LPC54114J256UK49_M4
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**
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** Compiler: IAR ANSI C/C++ Compiler for ARM
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** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016
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** Version: rev. 1.0, 2016-04-29
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** Build: b161227
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**
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** Abstract:
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** Linker file for the IAR ANSI C/C++ Compiler for ARM
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**
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** The Clear BSD License
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2017 NXP
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** All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted (subject to the limitations in the disclaimer below) provided
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** that the following conditions are met:
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**
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** 1. Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** 2. Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** 3. Neither the name of the copyright holder nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** ###################################################################
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*/
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define symbol m_interrupts_start = 0x00000000;
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define symbol m_interrupts_end = 0x000000DF;
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define symbol m_text_start = 0x000000E0;
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define symbol m_text_end = 0x0002FFFF;
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define symbol m_data_start = 0x20000000;
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define symbol m_data_end = 0x2000FFFF;
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if (isdefinedsymbol(__use_shmem__)) {
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define exported symbol rpmsg_sh_mem_start = 0x20026800;
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define exported symbol rpmsg_sh_mem_end = 0x20027FFF;
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}
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define symbol m_sramx_start = 0x04000000;
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define symbol m_sramx_end = 0x04007FFF;
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define exported symbol core1_image_start = 0x00030000;
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define exported symbol core1_image_end = 0x0003FFFF;
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define symbol __crp_start__ = 0x000002FC;
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define symbol __crp_end__ = 0x000002FF;
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define symbol __ram_iap_start__ = 0x2000FFE0;
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define symbol __ram_iap_end__ = 0x2000FFFF;
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/* Sizes */
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if (isdefinedsymbol(__stack_size__)) {
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define symbol __size_cstack__ = __stack_size__;
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} else {
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define symbol __size_cstack__ = 0x0400;
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}
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if (isdefinedsymbol(__heap_size__)) {
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define symbol __size_heap__ = __heap_size__;
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} else {
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define symbol __size_heap__ = 0x0800;
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}
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define exported symbol __RTT_HEAP_END = m_data_end;
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define memory mem with size = 4G;
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define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
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| mem:[from m_text_start to m_text_end]
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- mem:[from __crp_start__ to __crp_end__];
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define region DATA_region = mem:[from m_data_start to m_data_end]
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- mem:[from __ram_iap_start__-__size_cstack__ to __ram_iap_end__];
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define region CSTACK_region = mem:[from __ram_iap_start__-__size_cstack__ to __ram_iap_start__-1];
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define region SRAMX_region = mem:[from m_sramx_start to m_sramx_end];
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define region CRP_region = mem:[from __crp_start__ to __crp_end__];
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if (isdefinedsymbol(__use_shmem__)) {
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define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end];
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}
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define block CSTACK with alignment = 8, size = __size_cstack__ { };
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define block HEAP with alignment = 8, size = __size_heap__ { };
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define block RW { readwrite };
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define block ZI { zi };
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define region core1_region = mem:[from core1_image_start to core1_image_end];
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define block SEC_CORE_IMAGE_WBLOCK { section __sec_core };
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initialize by copy { readwrite };
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if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
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{
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// Required in a multi-threaded application
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initialize by copy with packing = none { section __DLIB_PERTHREAD };
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}
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do not initialize { section .noinit };
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if (isdefinedsymbol(__use_shmem__)) {
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do not initialize { section rpmsg_sh_mem_section };
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}
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place at address mem: m_interrupts_start { readonly section .intvec };
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place in TEXT_region { readonly };
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place in DATA_region { block RW };
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place in DATA_region { block ZI };
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place in DATA_region { last block HEAP };
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place in SRAMX_region { section sramx };
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place in CSTACK_region { block CSTACK };
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place in CRP_region { section .crp };
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if (isdefinedsymbol(__use_shmem__)) {
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place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section };
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}
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place in core1_region { block SEC_CORE_IMAGE_WBLOCK };
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