650 lines
20 KiB
C
650 lines
20 KiB
C
/**************************************************************************//**
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* @file core_cm4_simd.h
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* @brief CMSIS Cortex-M4 SIMD Header File
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* @version V3.01
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* @date 06. March 2012
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*
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* @note
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* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef __CORE_CM4_SIMD_H
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#define __CORE_CM4_SIMD_H
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/*******************************************************************************
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* Hardware Abstraction Layer
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******************************************************************************/
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/* ################### Compiler specific Intrinsics ########################### */
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/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
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Access to dedicated SIMD instructions
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@{
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*/
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#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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/* ARM armcc specific functions */
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/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
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#define __SADD8 __sadd8
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#define __QADD8 __qadd8
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#define __SHADD8 __shadd8
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#define __UADD8 __uadd8
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#define __UQADD8 __uqadd8
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#define __UHADD8 __uhadd8
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#define __SSUB8 __ssub8
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#define __QSUB8 __qsub8
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#define __SHSUB8 __shsub8
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#define __USUB8 __usub8
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#define __UQSUB8 __uqsub8
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#define __UHSUB8 __uhsub8
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#define __SADD16 __sadd16
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#define __QADD16 __qadd16
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#define __SHADD16 __shadd16
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#define __UADD16 __uadd16
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#define __UQADD16 __uqadd16
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#define __UHADD16 __uhadd16
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#define __SSUB16 __ssub16
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#define __QSUB16 __qsub16
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#define __SHSUB16 __shsub16
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#define __USUB16 __usub16
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#define __UQSUB16 __uqsub16
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#define __UHSUB16 __uhsub16
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#define __SASX __sasx
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#define __QASX __qasx
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#define __SHASX __shasx
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#define __UASX __uasx
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#define __UQASX __uqasx
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#define __UHASX __uhasx
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#define __SSAX __ssax
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#define __QSAX __qsax
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#define __SHSAX __shsax
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#define __USAX __usax
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#define __UQSAX __uqsax
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#define __UHSAX __uhsax
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#define __USAD8 __usad8
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#define __USADA8 __usada8
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#define __SSAT16 __ssat16
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#define __USAT16 __usat16
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#define __UXTB16 __uxtb16
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#define __UXTAB16 __uxtab16
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#define __SXTB16 __sxtb16
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#define __SXTAB16 __sxtab16
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#define __SMUAD __smuad
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#define __SMUADX __smuadx
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#define __SMLAD __smlad
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#define __SMLADX __smladx
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#define __SMLALD __smlald
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#define __SMLALDX __smlaldx
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#define __SMUSD __smusd
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#define __SMUSDX __smusdx
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#define __SMLSD __smlsd
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#define __SMLSDX __smlsdx
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#define __SMLSLD __smlsld
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#define __SMLSLDX __smlsldx
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#define __SEL __sel
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#define __QADD __qadd
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#define __QSUB __qsub
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#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
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((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
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#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
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((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
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/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
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#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
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/* IAR iccarm specific functions */
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/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
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#include <cmsis_iar.h>
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/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
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#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
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/* TI CCS specific functions */
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/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
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#include <cmsis_ccs.h>
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/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
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#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
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/* GNU gcc specific functions */
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/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
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{
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uint32_t result;
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__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
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return(result);
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}
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#define __SSAT16(ARG1,ARG2) \
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({ \
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uint32_t __RES, __ARG1 = (ARG1); \
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__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
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__RES; \
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})
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#define __USAT16(ARG1,ARG2) \
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({ \
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uint32_t __RES, __ARG1 = (ARG1); \
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__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
|
__RES; \
|
|
})
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
|
return(result);
|
|
}
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
|
return(result);
|
|
}
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
|
return(result);
|
|
}
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
|
return(result);
|
|
}
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
|
return(result);
|
|
}
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
|
return(result);
|
|
}
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
|
return(result);
|
|
}
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
|
return(result);
|
|
}
|
|
|
|
#define __SMLALD(ARG1,ARG2,ARG3) \
|
|
({ \
|
|
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
|
|
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
|
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
|
})
|
|
|
|
#define __SMLALDX(ARG1,ARG2,ARG3) \
|
|
({ \
|
|
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
|
|
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
|
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
|
})
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
|
return(result);
|
|
}
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
|
return(result);
|
|
}
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
|
return(result);
|
|
}
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
|
return(result);
|
|
}
|
|
|
|
#define __SMLSLD(ARG1,ARG2,ARG3) \
|
|
({ \
|
|
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
|
|
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
|
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
|
})
|
|
|
|
#define __SMLSLDX(ARG1,ARG2,ARG3) \
|
|
({ \
|
|
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
|
|
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
|
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
|
})
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
|
return(result);
|
|
}
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
|
return(result);
|
|
}
|
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
|
return(result);
|
|
}
|
|
|
|
#define __PKHBT(ARG1,ARG2,ARG3) \
|
|
({ \
|
|
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
|
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
|
__RES; \
|
|
})
|
|
|
|
#define __PKHTB(ARG1,ARG2,ARG3) \
|
|
({ \
|
|
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
|
if (ARG3 == 0) \
|
|
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
|
else \
|
|
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
|
__RES; \
|
|
})
|
|
|
|
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
|
|
|
|
|
|
|
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
|
/* TASKING carm specific functions */
|
|
|
|
|
|
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
|
/* not yet supported */
|
|
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
|
|
|
|
|
#endif
|
|
|
|
/*@} end of group CMSIS_SIMD_intrinsics */
|
|
|
|
|
|
#endif /* __CORE_CM4_SIMD_H */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|