320 lines
7.9 KiB
C
320 lines
7.9 KiB
C
#include <rthw.h>
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#include <rtthread.h>
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#include "io.h"
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#include <asm/ppc4xx-intvec.h>
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#define UART0_BASE 0xef600300
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#define UART1_BASE 0xef600400
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#define UCR0_MASK 0x0000007f
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#define UCR1_MASK 0x00007f00
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#define UCR0_UDIV_POS 0
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#define UCR1_UDIV_POS 8
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#define UDIV_MAX 127
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#define UART_RBR 0x00
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#define UART_THR 0x00
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#define UART_IER 0x01
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#define UART_IIR 0x02
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#define UART_FCR 0x02
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#define UART_LCR 0x03
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#define UART_MCR 0x04
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#define UART_LSR 0x05
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#define UART_MSR 0x06
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#define UART_SCR 0x07
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#define UART_DLL 0x00
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#define UART_DLM 0x01
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/*-----------------------------------------------------------------------------+
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| Line Status Register.
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+-----------------------------------------------------------------------------*/
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#define asyncLSRDataReady1 0x01
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#define asyncLSROverrunError1 0x02
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#define asyncLSRParityError1 0x04
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#define asyncLSRFramingError1 0x08
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#define asyncLSRBreakInterrupt1 0x10
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#define asyncLSRTxHoldEmpty1 0x20
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#define asyncLSRTxShiftEmpty1 0x40
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#define asyncLSRRxFifoError1 0x80
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/* PPC405 serial device */
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struct rt_ppc405_serial
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{
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/* inherit from device */
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struct rt_device parent;
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rt_uint32_t hw_base;
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rt_uint32_t irqno;
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rt_uint32_t baudrate;
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/* reception field */
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rt_uint16_t save_index, read_index;
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rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
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};
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struct rt_ppc405_serial ppc405_serial;
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/* serial character device */
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static rt_err_t rt_serial_init (rt_device_t dev)
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{
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return RT_EOK;
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}
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static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
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{
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struct rt_ppc405_serial* device;
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device = (struct rt_ppc405_serial*) dev;
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RT_ASSERT(device != RT_NULL);
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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/* Enable "RX Data Available" Interrupt on UART */
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out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01);
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/* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
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out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1);
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/* init UART rx interrupt */
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rt_hw_interrupt_unmask(device->irqno);
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}
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return RT_EOK;
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}
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static rt_err_t rt_serial_close(rt_device_t dev)
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{
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struct rt_ppc405_serial* device;
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device = (struct rt_ppc405_serial*) dev;
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RT_ASSERT(device != RT_NULL);
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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/* mask UART rx interrupt */
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rt_hw_interrupt_mask(device->irqno);
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}
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return RT_EOK;
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}
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static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
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{
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return RT_EOK;
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}
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static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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{
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rt_uint8_t* ptr;
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struct rt_ppc405_serial* device;
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device = (struct rt_ppc405_serial*) dev;
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RT_ASSERT(device != RT_NULL);
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/* point to buffer */
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ptr = (rt_uint8_t*) buffer;
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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while (size)
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{
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/* interrupt receive */
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rt_base_t level;
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/* disable interrupt */
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level = rt_hw_interrupt_disable();
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if (device->read_index != device->save_index)
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{
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*ptr = device->rx_buffer[device->read_index];
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device->read_index ++;
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if (device->read_index >= RT_UART_RX_BUFFER_SIZE)
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device->read_index = 0;
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}
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else
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{
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/* no data in rx buffer */
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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break;
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}
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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ptr ++; size --;
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}
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return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
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}
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else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
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{
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/* not support right now */
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RT_ASSERT(0);
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}
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/* polling mode */
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RT_ASSERT(0);
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return (rt_size_t)ptr - (rt_size_t)buffer;
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}
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static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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{
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char *ptr;
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struct rt_ppc405_serial* device;
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device = (struct rt_ppc405_serial*) dev;
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RT_ASSERT(device != RT_NULL);
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if (dev->flag & RT_DEVICE_FLAG_INT_TX)
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{
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/* not support */
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RT_ASSERT(0);
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}
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else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
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{
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/* not support */
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RT_ASSERT(0);
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}
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/* polling write */
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ptr = (char *)buffer;
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if (dev->flag & RT_DEVICE_FLAG_STREAM)
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{
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/* stream mode */
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while (size)
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{
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if (*ptr == '\n')
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{
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while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
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out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r');
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}
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while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
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out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr);
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ptr ++;
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size --;
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}
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}
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else
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{
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while (size)
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{
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while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
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out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr);
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ptr ++;
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size --;
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}
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}
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return (rt_size_t) ptr - (rt_size_t) buffer;
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}
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void rt_serial_set_baudrate(struct rt_ppc405_serial* device)
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{
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rt_uint32_t bdiv;
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bdiv = 115200;
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out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv); /* set baudrate divisor */
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out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
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}
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void rt_serial_isr(int irqno, void* param)
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{
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unsigned char status;
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struct rt_ppc405_serial *device;
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device = (struct rt_ppc405_serial*) param;
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status = in_8((rt_uint8_t *)device->hw_base + UART_LSR);
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if (status & 0x01)
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{
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rt_base_t level;
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while (status & 0x01)
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{
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/* disable interrupt */
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level = rt_hw_interrupt_disable();
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/* read character */
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device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base));
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device->save_index ++;
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if (device->save_index >= RT_UART_RX_BUFFER_SIZE)
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device->save_index = 0;
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/* if the next position is read index, discard this 'read char' */
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if (device->save_index == device->read_index)
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{
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device->read_index ++;
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if (device->read_index >= RT_UART_RX_BUFFER_SIZE)
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device->read_index = 0;
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}
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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/* check error */
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if ((status & ( asyncLSRFramingError1 |
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asyncLSROverrunError1 |
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asyncLSRParityError1 |
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asyncLSRBreakInterrupt1 )) != 0)
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{
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out_8((rt_uint8_t *)device->hw_base + UART_LSR,
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asyncLSRFramingError1 |
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asyncLSROverrunError1 |
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asyncLSRParityError1 |
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asyncLSRBreakInterrupt1);
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}
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status = in_8((rt_uint8_t *)device->hw_base + UART_LSR);
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}
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/* invoke callback */
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if(device->parent.rx_indicate != RT_NULL)
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{
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device->parent.rx_indicate(&device->parent, 1);
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}
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}
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}
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void rt_hw_serial_init(void)
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{
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volatile rt_uint8_t val;
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struct rt_ppc405_serial* device;
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device = (struct rt_ppc405_serial*) &ppc405_serial;
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device->parent.type = RT_Device_Class_Char;
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device->hw_base = UART0_BASE;
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device->baudrate = 115200;
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device->irqno = VECNUM_U0;
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rt_hw_interrupt_install(device->irqno, rt_serial_isr, device, "serial"); /* install isr */
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rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer));
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device->read_index = device->save_index = 0;
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out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80); /* set DLAB bit */
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/* setup baudrate */
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rt_serial_set_baudrate(device);
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out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
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out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00); /* disable FIFO */
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out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00); /* no modem control DTR RTS */
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val = in_8((rt_uint8_t *)device->hw_base + UART_LSR); /* clear line status */
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val = in_8((rt_uint8_t *)device->hw_base + UART_RBR); /* read receive buffer */
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out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00); /* set scratchpad */
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out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00); /* set interrupt enable reg */
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device->parent.type = RT_Device_Class_Char;
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device->parent.init = rt_serial_init;
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device->parent.open = rt_serial_open;
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device->parent.close = rt_serial_close;
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device->parent.read = rt_serial_read;
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device->parent.write = rt_serial_write;
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device->parent.control = rt_serial_control;
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device->parent.user_data = RT_NULL;
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rt_device_register(&device->parent,
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"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
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}
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