79 lines
2.9 KiB
C
79 lines
2.9 KiB
C
/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-02-20 bigmagic first version
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*/
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#ifndef __MMU_H__
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#define __MMU_H__
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/*
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* CR1 bits (CP#15 CR1)
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*/
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_C (1 << 2) /* Dcache enable */
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#define CR_W (1 << 3) /* Write buffer enable */
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#define CR_P (1 << 4) /* 32-bit exception handler */
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#define CR_D (1 << 5) /* 32-bit data address range */
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#define CR_L (1 << 6) /* Implementation defined */
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#define CR_B (1 << 7) /* Big endian */
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#define CR_S (1 << 8) /* System MMU protection */
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#define CR_R (1 << 9) /* ROM MMU protection */
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#define CR_F (1 << 10) /* Implementation defined */
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#define CR_Z (1 << 11) /* Implementation defined */
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#define CR_I (1 << 12) /* Icache enable */
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#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
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#define CR_RR (1 << 14) /* Round Robin cache replacement */
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#define CR_L4 (1 << 15) /* LDR pc can set T bit */
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#define CR_DT (1 << 16)
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#define CR_IT (1 << 18)
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#define CR_ST (1 << 19)
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#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
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#define CR_U (1 << 22) /* Unaligned access operation */
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#define CR_XP (1 << 23) /* Extended page tables */
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#define CR_VE (1 << 24) /* Vectored interrupts */
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#define CR_EE (1 << 25) /* Exception (Big) Endian */
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#define CR_TRE (1 << 28) /* TEX remap enable */
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#define CR_AFE (1 << 29) /* Access flag enable */
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#define CR_TE (1 << 30) /* Thumb exception enable */
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#define MMU_LEVEL_MASK 0x1ffUL
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#define MMU_MAP_ERROR_VANOTALIGN -1
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#define MMU_MAP_ERROR_PANOTALIGN -2
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#define MMU_MAP_ERROR_NOPAGE -3
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#define MMU_MAP_ERROR_CONFLICT -4
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#define MEM_ATTR_MEMORY ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2))
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#define MEM_ATTR_IO ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2))
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#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000)
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void mmu_init(void);
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void mmu_enable(void);
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int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr);
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void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr);
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//dcache
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void rt_hw_dcache_enable(void);
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void rt_hw_dcache_flush_all(void);
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void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size);
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void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size);
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void rt_hw_dcache_invalidate_all(void);
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void rt_hw_dcache_disable(void);
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//icache
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void rt_hw_icache_enable(void);
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void rt_hw_icache_invalidate_all(void);
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void rt_hw_icache_disable(void);
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#endif /*__MMU_H__*/
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