181 lines
4.3 KiB
C
181 lines
4.3 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-07-29 zdzn first version
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* 2021-12-28 GuEe-GUI add smp support
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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#include "drv_uart.h"
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#include "drv_timer.h"
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#include "gtimer.h"
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#include "cpuport.h"
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#include "interrupt.h"
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#include "mmu.h"
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#include "raspi.h"
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struct mem_desc platform_mem_desc[] =
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{
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{0, 0x6400000, 0, NORMAL_MEM},
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{0xc00000, 0xc01000, 0xc00000, DEVICE_MEM}, /* mbox */
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{0x3f000000, 0x3f200000, 0x3f000000, DEVICE_MEM}, /* timer */
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{0x3f200000, 0x3f216000, 0x3f200000, DEVICE_MEM}, /* uart */
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{0x40000000, 0x40200000, 0x40000000, DEVICE_MEM}, /* core timer */
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{0x3F300000, 0x3F301000, 0x3F300000, DEVICE_MEM}, /* sdio */
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{0x3f804000, 0x3f805000, 0x3f804000, DEVICE_MEM}, /* i2c0 */
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{0x3f205000, 0x3f206000, 0x3f205000, DEVICE_MEM}, /* i2c1 */
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};
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const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]);
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#if defined(BSP_USING_CORETIMER) || defined(RT_USING_SMP)
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static volatile rt_uint64_t timer_step;
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#define BSP_USING_CORETIMER
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#endif
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void rt_hw_timer_isr(int vector, void *parameter)
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{
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#ifdef BSP_USING_CORETIMER
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rt_hw_set_gtimer_val(timer_step);
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#else
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ARM_TIMER_IRQCLR = 0;
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#endif
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rt_tick_increase();
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}
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void rt_hw_timer_init(void)
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{
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rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
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rt_hw_interrupt_umask(IRQ_ARM_TIMER);
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#ifdef BSP_USING_CORETIMER
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__ISB();
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timer_step = rt_hw_get_gtimer_frq();
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__DSB();
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timer_step /= RT_TICK_PER_SECOND;
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rt_hw_gtimer_enable();
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rt_hw_set_gtimer_val(timer_step);
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#ifdef RT_USING_SMP
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core_timer_enable(rt_hw_cpu_id());
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#else
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core_timer_enable(0);
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#endif
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#else
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__DSB();
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/* timer_clock = apb_clock/(pre_divider + 1) */
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ARM_TIMER_PREDIV = (250 - 1);
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ARM_TIMER_RELOAD = 0;
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ARM_TIMER_LOAD = 0;
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ARM_TIMER_IRQCLR = 0;
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ARM_TIMER_CTRL = 0;
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ARM_TIMER_RELOAD = 10000;
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ARM_TIMER_LOAD = 10000;
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/* 23-bit counter, enable interrupt, enable timer */
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ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7);
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#endif
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}
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void idle_wfi(void)
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{
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asm volatile ("wfi");
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}
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/**
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* Initialize the Hardware related stuffs. Called from rtthread_startup()
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* after interrupt disabled.
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*/
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void rt_hw_board_init(void)
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{
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rt_hw_init_mmu_table(platform_mem_desc, platform_mem_desc_size);
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rt_hw_mmu_init();
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/* initialize hardware interrupt */
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rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
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/* initialize uart */
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rt_hw_uart_init(); // driver/drv_uart.c
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/* initialize timer for os tick */
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rt_hw_timer_init();
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rt_thread_idle_sethook(idle_wfi);
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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/* set console device */
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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#ifdef RT_USING_HEAP
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/* initialize memory system */
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rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
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rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
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#endif
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#ifdef RT_USING_SMP
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/* install IPI handle */
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rt_hw_ipi_handler_install(IRQ_ARM_MAILBOX, rt_scheduler_ipi_handler);
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rt_hw_interrupt_umask(IRQ_ARM_MAILBOX);
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enable_cpu_ipi_intr(0);
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#endif
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}
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#ifdef RT_USING_SMP
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static unsigned long cpu_release_paddr[] =
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{
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[0] = 0xd8,
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[1] = 0xe0,
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[2] = 0xe8,
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[3] = 0xf0,
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[4] = 0
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};
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void rt_hw_secondary_cpu_up(void)
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{
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int i;
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extern void secondary_cpu_start(void);
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for (i = 1; i < RT_CPUS_NR && cpu_release_paddr[i]; ++i)
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{
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__asm__ volatile ("str %0, [%1]"::"rZ"((unsigned long)secondary_cpu_start), "r"(cpu_release_paddr[i]));
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rt_hw_dcache_flush_range(cpu_release_paddr[i], sizeof(cpu_release_paddr[i]));
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__DSB();
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__SEV();
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}
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}
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void secondary_cpu_c_start(void)
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{
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int id = rt_hw_cpu_id();
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rt_hw_mmu_init();
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rt_hw_spin_lock(&_cpus_lock);
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rt_hw_vector_init();
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rt_hw_timer_init();
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enable_cpu_ipi_intr(id);
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rt_kprintf("\rcall cpu %d on success\n", id);
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rt_system_scheduler_start();
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}
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void rt_hw_secondary_cpu_idle_exec(void)
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{
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__WFE();
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}
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#endif
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