348 lines
7.9 KiB
C
348 lines
7.9 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-04-28 tyustli first version
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*
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*/
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#include <rtthread.h>
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#ifdef RT_USING_PWM
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#define LOG_TAG "drv.pwm"
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#include <drv_log.h>
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#include <rtdevice.h>
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#include <ioremap.h>
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#include "fsl_pwm.h"
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#include "drv_pwm.h"
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#include <drv_common.h>
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#include <drivers/rt_drv_pwm.h>
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#define PWM_SRC_CLK_FREQ CLOCK_GetFreq(kCLOCK_IpgClk)
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/* PWMPR register value of 0xffff has the same effect as 0xfffe */
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#define IMX_PWMPR_MAX 0xfffe
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#define NSEC_PER_MSEC 1000000
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#define NSEC_PER_SEC 1000
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#define MX3_PWMCR_SWR BIT(3)
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#define MX3_PWM_SWR_LOOP 5
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#define MX3_PWMSR_FIFOAV_EMPTY 0
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#define MX3_PWMSR_FIFOAV_1WORD 1
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#define MX3_PWMSR_FIFOAV_2WORDS 2
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#define MX3_PWMSR_FIFOAV_3WORDS 3
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#define MX3_PWMSR_FIFOAV_4WORDS 4
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#define MX3_PWMCR_STOPEN BIT(25)
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#define MX3_PWMCR_DOZEN BIT(24)
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#define MX3_PWMCR_WAITEN BIT(23)
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#define MX3_PWMCR_DBGEN BIT(22)
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#define MX3_PWMCR_BCTR BIT(21)
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#define MX3_PWMCR_HCTR BIT(20)
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#define MX3_PWMCR_CLKSRC BIT(17)
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#define MX3_PWMCR_EN BIT(0)
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static rt_err_t imx6ull_drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
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static struct rt_pwm_ops imxrt_drv_ops =
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{
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.control = imx6ull_drv_pwm_control
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};
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static void imx6ull_pwm_reset(PWM_Type *base)
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{
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int wait_count = 0;
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uint32_t cr = 0;
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base->PWMCR = MX3_PWMCR_SWR;
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do {
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rt_thread_mdelay(1);
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cr = base->PWMCR;
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} while ((cr & MX3_PWMCR_SWR) &&
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(wait_count++ < MX3_PWM_SWR_LOOP));
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if (cr & MX3_PWMCR_SWR)
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{
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LOG_E("software reset timeout\n");
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}
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}
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static void imx6ull_pwm_wait_fifo_slot(PWM_Type *base, struct rt_pwm_configuration *configuration)
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{
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unsigned int period_ms = 0;
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int fifoav = 0;
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uint32_t sr = 0;
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sr = base->PWMSR;
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fifoav = sr & 0x7;
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if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
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period_ms = configuration->period / NSEC_PER_MSEC;
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rt_thread_mdelay(period_ms);
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sr = base->PWMSR;
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if (fifoav == (sr & 0x7))
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{
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LOG_E("there is no free FIFO slot\n");
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}
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}
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}
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static rt_err_t imx6ull_pwm_enable(struct rt_device_pwm *device, rt_bool_t enable)
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{
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PWM_Type *base = (PWM_Type *)device->parent.user_data;
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if (!enable)
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{
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pwm_stop_timer(base);
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}
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else
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{
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pwm_start_timer(base);
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}
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return RT_EOK;
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}
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static rt_err_t imx6ull_pwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
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{
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uint32_t period = 0, prescaler = 0, val = 0;
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uint64_t tmp = 0;
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PWM_Type *base = (PWM_Type *)device->parent.user_data;
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uint32_t pwm_src_clk;
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pwm_src_clk = PWM_SRC_CLK_FREQ / 1000000;
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val = base->PWMCR;
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prescaler = ((val >> 4) & 0xfff)+1;
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val = base->PWMPR;
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period = val >= IMX_PWMPR_MAX ? IMX_PWMPR_MAX : val;
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tmp = NSEC_PER_SEC * (uint64_t)(period + 2) * prescaler;
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configuration->period = (tmp) / pwm_src_clk;
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val = base->PWMSAR;
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tmp = NSEC_PER_SEC * (uint64_t)(val) * prescaler;
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configuration->pulse = (tmp) / pwm_src_clk;
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return RT_EOK;
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}
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static rt_err_t imx6ull_pwm_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
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{
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RT_ASSERT(configuration->period > 0);
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RT_ASSERT(configuration->pulse <= configuration->period);
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PWM_Type *base = (PWM_Type *)device->parent.user_data;
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uint32_t period_cycles = 0, duty_cycles = 0, prescale = 0;
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uint32_t cr = 0;
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uint32_t pwm_src_clk = 0;
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pwm_src_clk = PWM_SRC_CLK_FREQ / 1000000;
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period_cycles = pwm_src_clk * configuration->period / NSEC_PER_SEC;
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prescale = period_cycles / 0x10000 + 1;
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period_cycles /= prescale;
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duty_cycles = configuration->pulse * pwm_src_clk / NSEC_PER_SEC ;
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duty_cycles /= prescale;
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/*
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* according to imx pwm RM, the real period value should be PERIOD
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* value in PWMPR plus 2.
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*/
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if (period_cycles > 2)
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{
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period_cycles -= 2;
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}
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else
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{
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period_cycles = 0;
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}
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if (((base->PWMCR) & 0x1) == 1)
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{
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imx6ull_pwm_wait_fifo_slot(base, configuration);
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}
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else
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{
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pwm_start_timer(base);
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imx6ull_pwm_reset(base);
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}
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base->PWMSAR = duty_cycles;
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base->PWMPR = period_cycles;
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cr = ((prescale -1 ) << 4) |
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MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | MX3_PWMCR_CLKSRC | MX3_PWMCR_DBGEN;
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cr |= MX3_PWMCR_EN;
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base->PWMCR = cr;
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return RT_EOK;
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}
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static rt_err_t imx6ull_drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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return imx6ull_pwm_enable(device, RT_TRUE);
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case PWM_CMD_DISABLE:
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return imx6ull_pwm_enable(device, RT_FALSE);
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case PWM_CMD_SET:
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return imx6ull_pwm_set(device, configuration);
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case PWM_CMD_GET:
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return imx6ull_pwm_get(device, configuration);
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default:
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return RT_EINVAL;
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}
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}
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static rt_err_t imx6ull_drv_pwm_init(PWM_Type *base)
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{
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pwm_config_t PwmConfig;
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pwm_get_default_config(&PwmConfig);
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if (pwm_init(base, &PwmConfig) == kStatus_Fail)
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{
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LOG_E("init pwm failed \n");
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return RT_ERROR;
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}
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return RT_EOK;
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}
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int imx6ull_pwm_gpio_init(void)
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{
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#ifdef BSP_USING_PWM1
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struct imx6ull_iomuxc gpio;
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gpio.muxRegister = 0x020E007C;
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gpio.muxMode = 0x0;
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gpio.inputRegister = 0x00000000;
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gpio.inputDaisy = 0x0;
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gpio.configRegister = 0x020E0308;
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gpio.inputOnfield = 0;
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gpio.configValue = IOMUXC_SW_PAD_CTL_PAD_DSE(2U) | IOMUXC_SW_PAD_CTL_PAD_SPEED(2U);
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imx6ull_gpio_init(&gpio);
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#endif
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return 0;
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}
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int rt_hw_pwm_init(void)
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{
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rt_err_t ret = RT_EOK;
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#ifdef BSP_USING_PWM1
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static struct rt_device_pwm pwm1_device;
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PWM_Type *pwm1_base;
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imx6ull_pwm_gpio_init();
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pwm1_base = (PWM_Type *)rt_ioremap((void*)PWM1, 0x1000);
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if (imx6ull_drv_pwm_init(pwm1_base) != RT_EOK)
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{
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LOG_E("init pwm1 failed\n");
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}
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ret = rt_device_pwm_register(&pwm1_device, "pwm1", &imxrt_drv_ops, pwm1_base);
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if (ret != RT_EOK)
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{
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LOG_E("%s register failed", "pwm1");
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}
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#endif /* BSP_USING_PWM1 */
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#ifdef BSP_USING_PWM2
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static struct rt_device_pwm pwm2_device;
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imx6ull_pwm_gpio_init();
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if (imx6ull_drv_pwm_init(PWM2) != RT_EOK)
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{
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LOG_E("init pwm2 failed\n");
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}
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ret = rt_device_pwm_register(&pwm2_device, "pwm2", &imxrt_drv_ops, PWM2);
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if (ret != RT_EOK)
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{
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LOG_E("%s register failed", "pwm2");
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}
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#endif /* BSP_USING_PWM2 */
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#ifdef BSP_USING_PWM3
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static struct rt_device_pwm pwm3_device;
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imx6ull_pwm_gpio_init();
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if (imx6ull_drv_pwm_init(PWM3) != RT_EOK)
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{
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LOG_E("init pwm3 failed\n");
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}
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ret = rt_device_pwm_register(&pwm3_device, "pwm3", &imxrt_drv_ops, PWM3);
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if (ret != RT_EOK)
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{
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LOG_E("%s register failed", "pwm3");
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}
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#endif /* BSP_USING_PWM3 */
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#ifdef BSP_USING_PWM4
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static struct rt_device_pwm pwm4_device;
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imx6ull_pwm_gpio_init();
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if (imx6ull_drv_pwm_init(PWM4) != RT_EOK)
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{
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LOG_E("init pwm4 failed\n");
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}
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ret = rt_device_pwm_register(&pwm4_device, "pwm4", &imxrt_drv_ops, PWM4);
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if (ret != RT_EOK)
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{
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LOG_E("%s register failed", "pwm4");
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}
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#endif /* BSP_USING_PWM4 */
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return ret;
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}
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INIT_DEVICE_EXPORT(rt_hw_pwm_init);
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int set_pwm_default(void)
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{
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int result = 0;
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struct rt_device_pwm *device = RT_NULL;
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device = (struct rt_device_pwm *)rt_device_find("pwm1");
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if (!device)
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{
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result = -RT_EIO;
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goto _exit;
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}
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result = rt_pwm_set(device, 1, 1000000, 500000);
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result = rt_pwm_enable(device, 1);
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_exit:
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return result;
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}
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INIT_APP_EXPORT(set_pwm_default);
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#endif /* BSP_USING_PWM */
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