351 lines
9.0 KiB
ArmAsm
351 lines
9.0 KiB
ArmAsm
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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* Copyright (c) 2021, Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020/08/20 zx.chen The T-HEAD RISC-V CPU E906 porting implementation
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* 2021/08/13 zx.chen update T-HEAD E9xx-series(E906/7/F/D/P) CPU porting code.
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*/
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#include "cpuport.h"
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#ifdef RT_USING_SMP
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#define rt_hw_interrupt_disable rt_hw_local_irq_disable
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#define rt_hw_interrupt_enable rt_hw_local_irq_enable
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#endif
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/*
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* Functions: vPortYield
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*/
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.global vPortYield
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.type vPortYield, %function
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vPortYield:
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li t0, 0xE080100C
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lb t1, (t0)
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li t2, 0x01
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or t1, t1, t2
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sb t1, (t0)
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ret
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/*
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread);
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* #else
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* void rt_hw_context_switch_to(rt_ubase_t to);
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* #endif
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* a0 --> to
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* a1 --> to_thread
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*/
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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/* save a0 to to_thread */
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la t0, rt_interrupt_to_thread
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STORE a0, (t0)
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/* save 0 to from_thread */
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la t0, rt_interrupt_from_thread
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li t1, 0
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STORE t1, (t0)
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/* set rt_thread_switch_interrupt_flag=1 */
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la t0, rt_thread_switch_interrupt_flag
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li t1, 1
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STORE t1, (t0)
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/* enable mexstatus SPUSHEN */
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#ifdef CONFIG_THEAD_EXT_SPUSHEN
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li t0, 0x10000
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csrs mexstatus, t0
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#endif
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csrw mscratch, sp
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/* set software interrupt */
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li t0, 0xE080100C
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lb t1, (t0)
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li t2, 0x01
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or t1, t1, t2
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sb t1, (t0)
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/* enable global interrup */
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csrsi mstatus, 8
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ret
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/*
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
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* #else
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* void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
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* #endif
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*
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* a0 --> from
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* a1 --> to
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* a2 --> to_thread
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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.globl rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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/* check rt_thread_switch_interrupt_flag */
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la t0, rt_thread_switch_interrupt_flag
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lw t1, (t0)
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li t2, 1
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beq t1, t2, .reswitch
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/* set rt_thread_switch_interrupt_flag=1 */
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STORE t2, (t0)
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/* update from_thread */
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la t0, rt_interrupt_from_thread
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STORE a0, (t0)
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.reswitch:
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/* update to_thread */
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la t0, rt_interrupt_to_thread
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STORE a1, (t0)
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/* set software interrupt */
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li t0, 0xE080100C
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lb t1, (t0)
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li t2, 0x01
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or t1, t1, t2
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sb t1, (t0)
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ret
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/*
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* PendSV_Handler
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*/
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.global PendSV_Handler
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.type PendSV_Handler, %function
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PendSV_Handler:
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/* check rt_thread_switch_interrupt_flag */
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sw t0, (-4)(sp)
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sw t1, (-8)(sp)
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la t0, rt_thread_switch_interrupt_flag
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lw t1, (t0)
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beqz t1, .pendsv_exit
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/* clear rt_thread_switch_interrupt_flag */
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li t1, 0x0
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sw t1, (t0)
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/* check rt_interrupt_from_thread */
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la t0, rt_interrupt_from_thread
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lw t1, (t0)
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beqz t1, .switch_to_thead
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/* restore from thread context t0,t1 */
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lw t0, (-4)(sp)
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lw t1, (-8)(sp)
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#ifdef ARCH_RISCV_FPU
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addi sp, sp, -32 * FREGBYTES
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FSTORE f0, 0 * FREGBYTES(sp)
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FSTORE f1, 1 * FREGBYTES(sp)
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FSTORE f2, 2 * FREGBYTES(sp)
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FSTORE f3, 3 * FREGBYTES(sp)
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FSTORE f4, 4 * FREGBYTES(sp)
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FSTORE f5, 5 * FREGBYTES(sp)
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FSTORE f6, 6 * FREGBYTES(sp)
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FSTORE f7, 7 * FREGBYTES(sp)
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FSTORE f8, 8 * FREGBYTES(sp)
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FSTORE f9, 9 * FREGBYTES(sp)
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FSTORE f10, 10 * FREGBYTES(sp)
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FSTORE f11, 11 * FREGBYTES(sp)
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FSTORE f12, 12 * FREGBYTES(sp)
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FSTORE f13, 13 * FREGBYTES(sp)
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FSTORE f14, 14 * FREGBYTES(sp)
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FSTORE f15, 15 * FREGBYTES(sp)
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FSTORE f16, 16 * FREGBYTES(sp)
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FSTORE f17, 17 * FREGBYTES(sp)
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FSTORE f18, 18 * FREGBYTES(sp)
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FSTORE f19, 19 * FREGBYTES(sp)
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FSTORE f20, 20 * FREGBYTES(sp)
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FSTORE f21, 21 * FREGBYTES(sp)
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FSTORE f22, 22 * FREGBYTES(sp)
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FSTORE f23, 23 * FREGBYTES(sp)
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FSTORE f24, 24 * FREGBYTES(sp)
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FSTORE f25, 25 * FREGBYTES(sp)
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FSTORE f26, 26 * FREGBYTES(sp)
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FSTORE f27, 27 * FREGBYTES(sp)
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FSTORE f28, 28 * FREGBYTES(sp)
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FSTORE f29, 29 * FREGBYTES(sp)
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FSTORE f30, 30 * FREGBYTES(sp)
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FSTORE f31, 31 * FREGBYTES(sp)
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#endif
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#ifdef ARCH_RISCV_DSP
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addi sp, sp, -33 * REGBYTES
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#else
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addi sp, sp, -32 * REGBYTES
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#endif
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STORE x1, 1 * REGBYTES(sp)
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csrr x1, mepc
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STORE x1, 0 * REGBYTES(sp)
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csrr x1, mstatus
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STORE x1, 2 * REGBYTES(sp)
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/* x3 don't need save */
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STORE x4, 4 * REGBYTES(sp)
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STORE x5, 5 * REGBYTES(sp)
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STORE x6, 6 * REGBYTES(sp)
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STORE x7, 7 * REGBYTES(sp)
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STORE x8, 8 * REGBYTES(sp)
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STORE x9, 9 * REGBYTES(sp)
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STORE x10, 10 * REGBYTES(sp)
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STORE x11, 11 * REGBYTES(sp)
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STORE x12, 12 * REGBYTES(sp)
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STORE x13, 13 * REGBYTES(sp)
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STORE x14, 14 * REGBYTES(sp)
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STORE x15, 15 * REGBYTES(sp)
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STORE x16, 16 * REGBYTES(sp)
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STORE x17, 17 * REGBYTES(sp)
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STORE x18, 18 * REGBYTES(sp)
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STORE x19, 19 * REGBYTES(sp)
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STORE x20, 20 * REGBYTES(sp)
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STORE x21, 21 * REGBYTES(sp)
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STORE x22, 22 * REGBYTES(sp)
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STORE x23, 23 * REGBYTES(sp)
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STORE x24, 24 * REGBYTES(sp)
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STORE x25, 25 * REGBYTES(sp)
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STORE x26, 26 * REGBYTES(sp)
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STORE x27, 27 * REGBYTES(sp)
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STORE x28, 28 * REGBYTES(sp)
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STORE x29, 29 * REGBYTES(sp)
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STORE x30, 30 * REGBYTES(sp)
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STORE x31, 31 * REGBYTES(sp)
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#ifdef ARCH_RISCV_DSP
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csrr t0, vxsat
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STORE t0, 32 * REGBYTES(sp)
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#endif
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/* store from_thread sp */
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la t0, rt_interrupt_from_thread
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lw t0, (t0)
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sw sp, (t0)
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.switch_to_thead:
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/* restore to thread context
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* sp(0) -> epc;
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* sp(1) -> ra;
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* sp(i) -> x(i+2)
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*/
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la t0, rt_interrupt_to_thread
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lw t0, (t0)
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LOAD sp, (t0)
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#ifdef ARCH_RISCV_DSP
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LOAD a1, 32 * REGBYTES(sp)
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csrw vxsat, a1
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#endif
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/* restore ra to mepc */
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LOAD a1, 0 * REGBYTES(sp)
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csrw mepc, a1
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LOAD x1, 1 * REGBYTES(sp)
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/* force to machine mode(MPP=11) */
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LOAD a1, 2 * REGBYTES(sp)
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csrw mstatus, a1
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/* x3 don't need restore */
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LOAD x4, 4 * REGBYTES(sp)
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LOAD x5, 5 * REGBYTES(sp)
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LOAD x6, 6 * REGBYTES(sp)
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LOAD x7, 7 * REGBYTES(sp)
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LOAD x8, 8 * REGBYTES(sp)
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LOAD x9, 9 * REGBYTES(sp)
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LOAD x10, 10 * REGBYTES(sp)
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LOAD x11, 11 * REGBYTES(sp)
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LOAD x12, 12 * REGBYTES(sp)
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LOAD x13, 13 * REGBYTES(sp)
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LOAD x14, 14 * REGBYTES(sp)
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LOAD x15, 15 * REGBYTES(sp)
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LOAD x16, 16 * REGBYTES(sp)
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LOAD x17, 17 * REGBYTES(sp)
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LOAD x18, 18 * REGBYTES(sp)
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LOAD x19, 19 * REGBYTES(sp)
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LOAD x20, 20 * REGBYTES(sp)
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LOAD x21, 21 * REGBYTES(sp)
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LOAD x22, 22 * REGBYTES(sp)
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LOAD x23, 23 * REGBYTES(sp)
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LOAD x24, 24 * REGBYTES(sp)
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LOAD x25, 25 * REGBYTES(sp)
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LOAD x26, 26 * REGBYTES(sp)
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LOAD x27, 27 * REGBYTES(sp)
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LOAD x28, 28 * REGBYTES(sp)
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LOAD x29, 29 * REGBYTES(sp)
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LOAD x30, 30 * REGBYTES(sp)
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LOAD x31, 31 * REGBYTES(sp)
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#ifdef ARCH_RISCV_DSP
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addi sp, sp, 33 * REGBYTES
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#else
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addi sp, sp, 32 * REGBYTES
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#endif
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#ifdef ARCH_RISCV_FPU
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FLOAD f0, 0 * FREGBYTES(sp)
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FLOAD f1, 1 * FREGBYTES(sp)
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FLOAD f2, 2 * FREGBYTES(sp)
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FLOAD f3, 3 * FREGBYTES(sp)
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FLOAD f4, 4 * FREGBYTES(sp)
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FLOAD f5, 5 * FREGBYTES(sp)
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FLOAD f6, 6 * FREGBYTES(sp)
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FLOAD f7, 7 * FREGBYTES(sp)
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FLOAD f8, 8 * FREGBYTES(sp)
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FLOAD f9, 9 * FREGBYTES(sp)
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FLOAD f10, 10 * FREGBYTES(sp)
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FLOAD f11, 11 * FREGBYTES(sp)
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FLOAD f12, 12 * FREGBYTES(sp)
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FLOAD f13, 13 * FREGBYTES(sp)
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FLOAD f14, 14 * FREGBYTES(sp)
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FLOAD f15, 15 * FREGBYTES(sp)
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FLOAD f16, 16 * FREGBYTES(sp)
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FLOAD f17, 17 * FREGBYTES(sp)
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FLOAD f18, 18 * FREGBYTES(sp)
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FLOAD f19, 19 * FREGBYTES(sp)
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FLOAD f20, 20 * FREGBYTES(sp)
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FLOAD f21, 21 * FREGBYTES(sp)
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FLOAD f22, 22 * FREGBYTES(sp)
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FLOAD f23, 23 * FREGBYTES(sp)
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FLOAD f24, 24 * FREGBYTES(sp)
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FLOAD f25, 25 * FREGBYTES(sp)
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FLOAD f26, 26 * FREGBYTES(sp)
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FLOAD f27, 27 * FREGBYTES(sp)
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FLOAD f28, 28 * FREGBYTES(sp)
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FLOAD f29, 29 * FREGBYTES(sp)
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FLOAD f30, 30 * FREGBYTES(sp)
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FLOAD f31, 31 * FREGBYTES(sp)
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addi sp, sp, 32 * FREGBYTES
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#endif
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.pendsv_exit:
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mret
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/*
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* rt_base_t rt_hw_interrupt_disable(void);
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*/
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.globl rt_hw_interrupt_disable
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.type rt_hw_interrupt_disable, %function
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rt_hw_interrupt_disable:
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csrrci a0, mstatus, 8
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ret
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.globl rt_hw_interrupt_enable
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.type rt_hw_interrupt_enable, %function
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rt_hw_interrupt_enable:
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csrw mstatus, a0
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ret
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