103 lines
4.0 KiB
C
103 lines
4.0 KiB
C
/*
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File Name : board_config.h
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Author : Yichip
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Version : V1.0
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Date : 2020/07/17
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Description : misc file.
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*/
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#include "misc.h"
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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/* Memory mapping of Cortex-M0 Hardware */
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#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
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#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
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#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
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typedef struct
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{
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__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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uint32_t RESERVED0;
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__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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uint32_t RESERVED1;
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__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
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__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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} SCB_Type;
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/**
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\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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*/
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typedef struct
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{
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__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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uint32_t RESERVED0[31U];
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__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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uint32_t RSERVED1[31U];
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__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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uint32_t RESERVED2[31U];
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__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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uint32_t RESERVED3[31U];
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uint32_t RESERVED4[64U];
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__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
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} NVIC_Type;
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#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */
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#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */
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/* The following MACROS handle generation of the register offset and byte masks */
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#define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL)
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#define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
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#define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
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/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
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#define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */
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#define __MPU_PRESENT 0 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/* End of group Configuration_of_CMSIS */
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uint32_t NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
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{
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if ((int32_t)(IRQn) < 0)
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{
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SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
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(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
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}
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else
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{
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NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
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(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
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}
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return SUCCESS;
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}
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#define SBC_ICSR_PENDSV_IRQ 28
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void trigger_PendSV(void)
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{
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SCB->ICSR |= (1 << SBC_ICSR_PENDSV_IRQ);
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}
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void NVIC_EnableIRQ(IRQn_Type IRQnx)
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{
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enable_intr((int)IRQnx);
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}
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void NVIC_DisableIRQ(IRQn_Type IRQnx)
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{
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disable_intr((int)IRQnx);
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}
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void soft_reset(void)
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{
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SYSCTRL_RST_EN |= 0x01;
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SYSCTRL_RESET = 0x55;
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while (1);
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}
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