199 lines
5.4 KiB
ArmAsm
199 lines
5.4 KiB
ArmAsm
/*
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* File : context.S
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2013, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-05 Bernard the first version
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* 2018-11-22 Jesven in the smp version, using macro to
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* define rt_hw_interrupt_enable and rt_hw_interrupt_disable
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* rt_hw_context_switch_interrupt switches to the new thread directly
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*/
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#include "rtconfig.h"
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.section .text, "ax"
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#ifdef RT_USING_SMP
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#define rt_hw_interrupt_disable rt_hw_local_irq_disable
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#define rt_hw_interrupt_enable rt_hw_local_irq_enable
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#endif
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/*
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* rt_base_t rt_hw_interrupt_disable();
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*/
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.globl rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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mrs r0, cpsr
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cpsid i
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bx lr
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.globl rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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msr cpsr, r0
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bx lr
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/*
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* void rt_hw_context_switch_to(rt_uint32 to);
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* r0 --> to
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*/
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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ldr sp, [r0] @ get new task stack pointer
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#ifdef RT_USING_SMP
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mov r0, r1
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bl rt_cpus_lock_status_restore
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#endif /*RT_USING_SMP*/
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#ifdef RT_USING_LWP
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ldmfd sp, {r13, r14}^ @ pop usr_sp usr_lr
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add sp, #8
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#endif
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ldmfd sp!, {r4} @ pop new task spsr
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msr spsr_cxsf, r4
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ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc
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.section .bss.share.isr
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_guest_switch_lvl:
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.word 0
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.section .text.isr, "ax"
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/*
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* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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* r0 --> from
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* r1 --> to
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC)
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stmfd sp!, {r0-r12, lr} @ push lr & register file
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mrs r4, cpsr
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tst lr, #0x01
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orrne r4, r4, #0x20 @ it's thumb code
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stmfd sp!, {r4} @ push cpsr
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#ifdef RT_USING_LWP
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stmfd sp, {r13, r14}^ @ push usr_sp usr_lr
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sub sp, #8
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#endif
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str sp, [r0] @ store sp in preempted tasks TCB
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ldr sp, [r1] @ get new task stack pointer
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#ifdef RT_USING_SMP
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mov r0, r2
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bl rt_cpus_lock_status_restore
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#endif /*RT_USING_SMP*/
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#ifdef RT_USING_LWP
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ldmfd sp, {r13, r14}^ @ pop usr_sp usr_lr
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add sp, #8
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#endif
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ldmfd sp!, {r4} @ pop new task cpsr to spsr
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msr spsr_cxsf, r4
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ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr
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/*
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* void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
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*/
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.equ Mode_USR, 0x10
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.equ Mode_FIQ, 0x11
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.equ Mode_IRQ, 0x12
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.equ Mode_SVC, 0x13
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.equ Mode_ABT, 0x17
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.equ Mode_UND, 0x1B
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.equ Mode_SYS, 0x1F
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.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
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.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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.globl rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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#ifdef RT_USING_SMP
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/* r0 :irq_mod context
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* r1 :addr of from_thread's sp
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* r2 :addr of to_thread's sp
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* r3 :to_thread's tcb
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*/
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@ r0 point to {r0-r3} in stack
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push {r1 - r3}
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mov r1, r0
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add r0, r0, #4*4
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ldmfd r0!, {r4-r12,lr}@ reload saved registers
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mrs r3, spsr @ get cpsr of interrupt thread
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sub r2, lr, #4 @ save old task's pc to r2
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msr cpsr_c, #I_Bit|F_Bit|Mode_SVC
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stmfd sp!, {r2} @ push old task's pc
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stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4
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ldmfd r1, {r4-r7} @ restore r0-r3 of the interrupt thread
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stmfd sp!, {r4-r7} @ push old task's r0-r3
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stmfd sp!, {r3} @ push old task's cpsr
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#ifdef RT_USING_LWP
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stmfd sp, {r13,r14}^ @push usr_sp usr_lr
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sub sp, #8
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#endif
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msr cpsr_c, #I_Bit|F_Bit|Mode_IRQ
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pop {r1 - r3}
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mov sp, r0
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msr cpsr_c, #I_Bit|F_Bit|Mode_SVC
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str sp, [r1]
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ldr sp, [r2]
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mov r0, r3
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bl rt_cpus_lock_status_restore
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#ifdef RT_USING_LWP
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ldmfd sp, {r13,r14}^ @pop usr_sp usr_lr
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add sp, #8
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#endif
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ldmfd sp!, {r4} @ pop new task's cpsr to spsr
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msr spsr_cxsf, r4
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ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
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#else /*RT_USING_SMP*/
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ldr r2, =rt_thread_switch_interrupt_flag
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ldr r3, [r2]
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cmp r3, #1
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beq _reswitch
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ldr ip, =rt_interrupt_from_thread @ set rt_interrupt_from_thread
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mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1
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str r0, [ip]
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str r3, [r2]
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_reswitch:
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ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread
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str r1, [r2]
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bx lr
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#endif /*RT_USING_SMP*/
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