130 lines
6.2 KiB
Markdown
130 lines
6.2 KiB
Markdown
# AXU4EV-E BSP (Board Support Package) Execution Instruction
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[中文页](README_zh.md) |
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## **Introduction**
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This document records the execution instruction of the BSP (board support package) for the AXU4EV-E development board.
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The document is covered in three parts:
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- AXU4EV-E Board Resources Introduction
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- Quickly Get Started
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- Advanced Features
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- BSP Migration
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By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
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## AXU4EV-E Resources Introduction
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ALINX AXU4EV-E: Xilinx Zynq UltraScale+ MPSOC XCZU4EV-1SFVC784I Ethernet FPGA development board, the SoM Core board is the smallest system, mainly composed of XCZU4EV-1SFVC784I + 5 DDR4 + eMMC + 1 QSPI FLASH. The Carrier board expands a wealth of peripheral interfaces for the core board, including 1 SATA M.2 interface, 1 DP output interface, 4 USB3.0 interfaces, 2 Gigabit Ethernet interfaces, 2 UART interfaces, 1 SD card interface, 2*40-pin Expansion Connectors for Modules, 2 CAN bus interfaces, 2 RS485 interfaces, 1 MIPI interface, Keys and LEDs. High-speed data exchange and transmission, data storage, pre-verification and post-application of data processing, video transmission processing, deep learning, artificial intelligence and industrial control, is a professional ZYNQ development platform. suitable for students, engineers and other groups engaged in the development of MPSoCs.
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For more details about this board, please refer to [Alinx Electronic Technology (Shanghai) Co.,Ltd.](http://www.alinx.com/en/)。
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## **Peripheral Condition**
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Each peripheral supporting condition for this BSP is as follows:
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| **Core** | **Support** | **Remark** |
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| :----------------- | :----------: | :------------------------------------- |
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| R5-CPU0 | Support | The R5-CPU0 is running the system |
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| **On-board Peripherals** | **Support** | **Remark** |
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| None | | |
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| **On-chip Peripherals** | **Support** | **Remark** |
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| GPIO | Support | |
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| UART | Support | UART0 |
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| TIMER | Support | TTC0 provides system clock |
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| EMMC | Support | SD0 Controller |
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| EMAC | Support | e0 Net Interface |
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## Execution Instruction
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### Quickly Get Started
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This BSP only support the GCC development environment. Here's an example to introduce how to run the system.
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#### Compile and Download
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1. Open the env tool under BSP. Enter `scons` to compile.
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2. After compiling, `rtthread-zynqmp-r5.elf` file will be generated in BSP directory.
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3. Use Xilinx Vitis to generate fsbl, and then create "Debug Configuration", select the `rtthread-zynqmp-r5.elf` file as the application.
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4. Use the debugger to connect the PC and the development board. Set the dial switch to JTAG to start. Then connect the power supply. Click start debugging or running.
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Since the compiler has debugging information by default (see rtconfig.py In BUILD, so when debugging in Xilinx Vitis, you can also open source files to set breakpoints for debugging.
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#### Software Solidification
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1. Open the env tool under BSP. Enter `scons` to compile.
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2. After compiling, `rtthread-zynqmp-r5.elf` file will be generated in BSP directory.
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3. Use Xilinx Vitis or Xilinx SDK to generate fsbl, and then use the bootgen tool provided by Xilinx to make fsbl BOOT.bin Documents.
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For example, use the command line:
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```
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bootgen -image ./output.bif -arch zynqmp -o ./BOOT.bin -w on
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```
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And the outpu.bif file could be：
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```
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//arch = zynqmp; split = false; format = BIN
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the_ROM_image:
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{
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[bootloader, destination_cpu = r5-0]./fsbl.elf
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[destination_cpu = r5-0, exception_level = el-3]./rtthread-zynqmp-r5.elf
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}
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```
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4. According to the document provided by Alinx, put BOOT.bin into SD card or burn to QSPI flash, set the startup mode through dial switch, and then connect the power supply to start.
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#### Running Results
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Once the project is successfully downloaded, the system runs automatically.
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Connect the serial port of the board to PC, communicate with it via a serial terminal tool (115200bps, 8N1). Restart the board and the startup information of RT-Thread will be observed:
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```bash
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\ | /
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- RT - Thread Operating System
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/ | \ 4.0.3 build Nov 27 2020
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2006 - 2020 Copyright by rt-thread team
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msh />
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```
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### **Advanced Features**
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This BSP enables EMMC driver and DFS file system by default. If you need to use a file system, you can format and mount it by yourself.
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This BSP is enabled and configured with net interface driver and LwIP protocol stack by default, and note the following configuration:
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1. Note that `RT_LWIP_PBUF_NUM` is set to at least 256
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2. Note that `RT_ LWIP_ MEM_ Alignment` is set to 32. If the version other than lwip 2.0.2 in RTT is used, the `MEM_ALIGNMENT` in `lwipopts.h` needs to be modified manually because the macro is not used in other versions.
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## BSP Migration
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If you need to ported the BSP to another development board of Xilinx Zynq UltraScale+ MPSOC development platform, it is also convenient. The main modifications are as follows:
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1. Memory: `psu_r5_ddr_0_MEM_0` in `zynqmp-r5.ld` and `HEAP_END` in `board.h ` (if DDR memory is less than 2G)
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2. Main Frequency: `XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ` in `zynqmp-r5.h`
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3. Pin and Frequency of Serial Port: `rxmio`, `txmio` and `XPAR_PSU_UART_0_UART_CLK_FREQ_HZ` in `drv_uart.c`
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4. Timer Frequency: `XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ` in `drv_timer.c`
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5. SD Controller: Block device driver initialization in `drv_sdcard.c`
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6. Net interface: If the PHY chip used is not in the range of driver support, it may be necessary to realize the rate identification function of the corresponding chip in `xemacpsif_physpeed.c`. You can refer to the corresponding tutorial of Alinx.
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The parameter macro definition in `xparameters.h` does not need to be modified manually. You can directly copy the `xparameters.h` file of the development board generated in Xilinx Vitis.
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## Attention
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-None
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## Contact
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Maintainer:
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- [Wang Huachen](https://github.com/Wang-Huachen/) |