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2322f0154e
Confirmed with milkv, only the sd card version is sold by default for duo in the market. The spi pins are provided through stamp holes, so that users can solder the corresponding components on their baseboard during secondary development. In order to simplify maintenance work, the mainline will only support the sd-card version and no longer support spinor/spinand. Updated config files the same in this patch. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
349 lines
8.4 KiB
C
349 lines
8.4 KiB
C
/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-03-28 qiujingbao first version
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* 2024/06/08 flyingcys fix transmission failure
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include <rtdevice.h>
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#include "board.h"
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#include "drv_spi.h"
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#include "drv_pinmux.h"
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#include "drv_ioremap.h"
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#define DBG_LEVEL DBG_LOG
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#include <rtdbg.h>
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#define LOG_TAG "drv.spi"
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struct _device_spi
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{
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struct rt_spi_bus spi_bus;
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struct dw_spi dws;
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char *device_name;
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};
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static struct _device_spi _spi_obj[] =
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{
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#ifdef BSP_USING_SPI0
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{
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.dws.regs = (void *)DW_SPI0_BASE,
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.dws.irq = DW_SPI0_IRQn,
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.dws.index = 0,
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.device_name = "spi0",
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},
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#endif /* BSP_USING_SPI0 */
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#ifdef BSP_USING_SPI1
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{
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.dws.regs = (void *)DW_SPI1_BASE,
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.dws.irq = DW_SPI1_IRQn,
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.dws.index = 0,
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.device_name = "spi1",
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},
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#endif /* BSP_USING_SPI1 */
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#ifdef BSP_USING_SPI2
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{
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.dws.regs = (void *)DW_SPI2_BASE,
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.dws.irq = DW_SPI2_IRQn,
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.dws.index = 0,
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.device_name = "spi2",
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},
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#endif /* BSP_USING_SPI2 */
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#ifdef BSP_USING_SPI3
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{
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.dws.regs = (void *)DW_SPI3_BASE,
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.dws.irq = DW_SPI3_IRQn,
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.dws.index = 0,
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.device_name = "spi3",
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},
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#endif /* BSP_USING_SPI3 */
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};
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static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
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{
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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RT_ASSERT(device->bus->parent.user_data != RT_NULL);
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RT_ASSERT(cfg != RT_NULL);
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rt_err_t ret = RT_EOK;
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struct _device_spi *spi = (struct _device_spi *)device->bus->parent.user_data;
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struct dw_spi *dws = &spi->dws;
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rt_uint8_t mode;
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LOG_D("spi_configure input");
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/* set cs low when spi idle */
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writel(0, (void *)0x030001d0);
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if (cfg->mode & RT_SPI_SLAVE)
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{
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LOG_E("invalid mode: %d", cfg->mode);
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return -RT_EINVAL;
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}
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spi_reset_chip(dws);
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spi_hw_init(dws);
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spi_enable_chip(dws, 0);
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LOG_D("cfg->max_hz: %d", cfg->max_hz);
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dw_spi_set_clock(dws, SPI_REF_CLK, cfg->max_hz);
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LOG_D("cfg->data_width: %d", cfg->data_width);
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if (dw_spi_set_data_frame_len(dws, (uint32_t)cfg->data_width) < 0)
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{
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LOG_E("dw_spi_set_data_frame_len failed...\n");
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return -RT_ERROR;
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}
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LOG_D("cfg->mode: %08x", cfg->mode);
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switch (cfg->mode & RT_SPI_MODE_3)
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{
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case RT_SPI_MODE_0:
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mode = SPI_FORMAT_CPOL0_CPHA0;
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break;
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case RT_SPI_MODE_1:
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mode = SPI_FORMAT_CPOL0_CPHA1;
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break;
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case RT_SPI_MODE_2:
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mode = SPI_FORMAT_CPOL1_CPHA0;
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break;
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case RT_SPI_MODE_3:
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mode = SPI_FORMAT_CPOL1_CPHA1;
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break;
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default:
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LOG_E("spi configure mode error %x\n", cfg->mode);
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break;
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}
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dw_spi_set_polarity_and_phase(dws, mode);
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dw_spi_set_cs(dws, 1, 0);
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spi_enable_chip(dws, 1);
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return RT_EOK;
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}
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static rt_err_t dw_spi_transfer_one(struct dw_spi *dws, const void *tx_buf, void *rx_buf, uint32_t len, enum transfer_type tran_type)
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{
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uint8_t imask = 0;
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uint16_t txlevel = 0;
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dws->tx = NULL;
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dws->tx_end = NULL;
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dws->rx = NULL;
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dws->rx_end = NULL;
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if (tx_buf != NULL) {
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dws->tx = tx_buf;
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dws->tx_end = dws->tx + len;
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}
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if (rx_buf != NULL) {
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dws->rx = rx_buf;
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dws->rx_end = dws->rx + len;
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}
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dws->rx_len = len / dws->n_bytes;
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dws->tx_len = len / dws->n_bytes;
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spi_enable_chip(dws, 0);
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/* For poll mode just disable all interrupts */
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spi_mask_intr(dws, 0xff);
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/* set tran mode */
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set_tran_mode(dws);
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/* cs0 */
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dw_spi_set_cs(dws, true, 0);
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/* enable spi */
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spi_enable_chip(dws, 1);
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rt_hw_us_delay(10);
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if (tran_type == POLL_TRAN)
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{
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if (poll_transfer(dws) < 0)
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return -RT_ERROR;
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}
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else
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{
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return -RT_ENOSYS;
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}
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return RT_EOK;
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}
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static rt_ssize_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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RT_ASSERT(device->bus->parent.user_data != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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struct _device_spi *spi = (struct _device_spi *)device->bus->parent.user_data;
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struct dw_spi *dws = &spi->dws;
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int32_t ret = 0;
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if (message->send_buf && message->recv_buf)
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{
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ret = dw_spi_transfer_one(dws, message->send_buf, message->recv_buf, message->length, POLL_TRAN);
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}
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else if (message->send_buf)
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{
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ret = dw_spi_transfer_one(dws, message->send_buf, RT_NULL, message->length, POLL_TRAN);
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}
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else if (message->recv_buf)
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{
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ret = dw_spi_transfer_one(dws, RT_NULL, message->recv_buf, message->length, POLL_TRAN);
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}
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return message->length;
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}
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static const struct rt_spi_ops _spi_ops =
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{
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.configure = spi_configure,
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.xfer = spi_xfer,
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};
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#if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO256M)
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// For Duo / Duo 256m, only SPI2 are exported on board.
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#ifdef BSP_USING_SPI0
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static const char *pinname_whitelist_spi0_sck[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi0_sdo[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi0_sdi[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi0_cs[] = {
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NULL,
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};
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#endif
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#ifdef BSP_USING_SPI1
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static const char *pinname_whitelist_spi1_sck[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi1_sdo[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi1_sdi[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi1_cs[] = {
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NULL,
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};
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#endif
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#ifdef BSP_USING_SPI2
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static const char *pinname_whitelist_spi2_sck[] = {
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"SD1_CLK",
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NULL,
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};
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static const char *pinname_whitelist_spi2_sdo[] = {
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"SD1_CMD",
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NULL,
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};
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static const char *pinname_whitelist_spi2_sdi[] = {
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"SD1_D0",
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NULL,
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};
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static const char *pinname_whitelist_spi2_cs[] = {
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"SD1_D3",
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NULL,
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};
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#endif
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#ifdef BSP_USING_SPI3
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static const char *pinname_whitelist_spi3_sck[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi3_sdo[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi3_sdi[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi3_cs[] = {
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NULL,
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};
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#endif
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#else
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#error "Unsupported board type!"
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#endif
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static void rt_hw_spi_pinmux_config()
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{
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#ifdef BSP_USING_SPI0
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pinmux_config(BSP_SPI0_SCK_PINNAME, SPI0_SCK, pinname_whitelist_spi0_sck);
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pinmux_config(BSP_SPI0_SDO_PINNAME, SPI0_SDO, pinname_whitelist_spi0_sdo);
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pinmux_config(BSP_SPI0_SDI_PINNAME, SPI0_SDI, pinname_whitelist_spi0_sdi);
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pinmux_config(BSP_SPI0_CS_PINNAME, SPI0_CS_X, pinname_whitelist_spi0_cs);
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#endif /* BSP_USING_SPI0 */
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#ifdef BSP_USING_SPI1
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pinmux_config(BSP_SPI1_SCK_PINNAME, SPI1_SCK, pinname_whitelist_spi1_sck);
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pinmux_config(BSP_SPI1_SDO_PINNAME, SPI1_SDO, pinname_whitelist_spi1_sdo);
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pinmux_config(BSP_SPI1_SDI_PINNAME, SPI1_SDI, pinname_whitelist_spi1_sdi);
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pinmux_config(BSP_SPI1_CS_PINNAME, SPI1_CS_X, pinname_whitelist_spi1_cs);
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#endif /* BSP_USING_SPI1 */
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#ifdef BSP_USING_SPI2
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pinmux_config(BSP_SPI2_SCK_PINNAME, SPI2_SCK, pinname_whitelist_spi2_sck);
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pinmux_config(BSP_SPI2_SDO_PINNAME, SPI2_SDO, pinname_whitelist_spi2_sdo);
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pinmux_config(BSP_SPI2_SDI_PINNAME, SPI2_SDI, pinname_whitelist_spi2_sdi);
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pinmux_config(BSP_SPI2_CS_PINNAME, SPI2_CS_X, pinname_whitelist_spi2_cs);
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#endif /* BSP_USING_SPI2 */
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#ifdef BSP_USING_SPI3
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pinmux_config(BSP_SPI3_SCK_PINNAME, SPI3_SCK, pinname_whitelist_spi3_sck);
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pinmux_config(BSP_SPI3_SDO_PINNAME, SPI3_SDO, pinname_whitelist_spi3_sdo);
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pinmux_config(BSP_SPI3_SDI_PINNAME, SPI3_SDI, pinname_whitelist_spi3_sdi);
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pinmux_config(BSP_SPI3_CS_PINNAME, SPI3_CS_X, pinname_whitelist_spi3_cs);
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#endif /* BSP_USING_SPI3 */
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}
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int rt_hw_spi_init(void)
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{
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rt_err_t ret = RT_EOK;
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struct dw_spi *dws;
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rt_hw_spi_pinmux_config();
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for (rt_size_t i = 0; i < sizeof(_spi_obj) / sizeof(struct _device_spi); i++)
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{
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_spi_obj[i].base_addr = (rt_ubase_t)DRV_IOREMAP((void *)_spi_obj[i].base_addr, 0x1000);
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_spi_obj[i].spi_bus.parent.user_data = (void *)&_spi_obj[i];
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ret = rt_spi_bus_register(&_spi_obj[i].spi_bus, _spi_obj[i].device_name, &_spi_ops);
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}
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RT_ASSERT(ret == RT_EOK);
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return ret;
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}
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INIT_DEVICE_EXPORT(rt_hw_spi_init);
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