267 lines
8.1 KiB
C
267 lines
8.1 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "synopsys_emac.h"
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#include "gd32f4xx_enet.h"
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/* The state of enet initialization */
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volatile uint32_t enet_init_state = 0;
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/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
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extern EMAC_DMADESCTypeDef *DMATxDescToSet;
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extern EMAC_DMADESCTypeDef *DMARxDescToGet;
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/**
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* Initializes the ETHERNET peripheral according to the specified
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*/
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rt_uint32_t EMAC_init(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t SystemCoreClock)
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{
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/*-------------------------------- Reset ethernet -------------------------------*/
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enet_deinit();
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enet_software_reset();
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/* configure the parameters which are usually less cared for enet initialization */
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enet_initpara_config(HALFDUPLEX_OPTION, ENET_CARRIERSENSE_DISABLE|ENET_RECEIVEOWN_ENABLE|ENET_RETRYTRANSMISSION_DISABLE|ENET_BACKOFFLIMIT_10|ENET_DEFERRALCHECK_DISABLE);
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/*-------------------------------- Initialize ENET ------------------------------*/
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enet_init_state = enet_init(ENET_AUTO_NEGOTIATION, ENET_AUTOCHECKSUM_DROP_FAILFRAMES, ENET_BROADCAST_FRAMES_PASS);
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/* Return Ethernet configuration success */
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return EMAC_SUCCESS;
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}
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/**
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* Enables or disables the specified ETHERNET DMA interrupts.
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*/
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void EMAC_INT_config(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t EMAC_DMA_IT, rt_bool_t NewState)
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{
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if (NewState)
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{
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/* Enable the selected ETHERNET DMA interrupts */
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ETHERNET_MAC->IER |= EMAC_DMA_IT;
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}
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else
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{
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/* Disable the selected ETHERNET DMA interrupts */
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ETHERNET_MAC->IER &=(~(rt_uint32_t)EMAC_DMA_IT);
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}
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}
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/**
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* Configures the selected MAC address.
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*/
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void EMAC_MAC_Addr_config(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t MacAddr, rt_uint8_t *Addr)
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{
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rt_uint32_t value;
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/* Calculate the selectecd MAC address high register */
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value = ((rt_uint32_t)Addr[5] << 8) | (rt_uint32_t)Addr[4];
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/* Load the selectecd MAC address high register */
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//(*(volatile rt_uint32_t *) (EMAC_MAC_ADDR_HBASE + MacAddr)) = value;
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ETHERNET_MAC->MARs[MacAddr].MARH = value;
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/* Calculate the selectecd MAC address low register */
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value = ((rt_uint32_t)Addr[3] << 24) | ((rt_uint32_t)Addr[2] << 16) | ((rt_uint32_t)Addr[1] << 8) | Addr[0];
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/* Load the selectecd MAC address low register */
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//(*(volatile rt_uint32_t *) (EMAC_MAC_ADDR_LBASE + MacAddr)) = value;
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ETHERNET_MAC->MARs[MacAddr].MARL = value;
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}
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/**
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* Enables or disables the MAC transmission.
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*/
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void EMAC_MACTransmissionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
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{
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if (NewState)
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{
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/* Enable the MAC transmission */
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ETHERNET_MAC->MCR |= EMAC_MACCR_TE;
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}
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else
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{
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/* Disable the MAC transmission */
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ETHERNET_MAC->MCR &= ~EMAC_MACCR_TE;
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}
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}
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/**
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* Clears the ETHERNET transmit FIFO.
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*/
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void EMAC_FlushTransmitFIFO(struct rt_synopsys_eth * ETHERNET_MAC)
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{
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/* Set the Flush Transmit FIFO bit */
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ETHERNET_MAC->OMR |= EMAC_DMAOMR_FTF;
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}
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/**
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* Enables or disables the MAC reception.
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*/
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void EMAC_MACReceptionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
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{
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if (NewState)
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{
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/* Enable the MAC reception */
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ETHERNET_MAC->MCR |= EMAC_MACCR_RE;
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}
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else
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{
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/* Disable the MAC reception */
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ETHERNET_MAC->MCR &= ~EMAC_MACCR_RE;
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}
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}
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/**
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* Enables or disables the DMA transmission.
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*/
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void EMAC_DMATransmissionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
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{
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if (NewState)
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{
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/* Enable the DMA transmission */
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ETHERNET_MAC->OMR |= EMAC_DMAOMR_ST;
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}
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else
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{
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/* Disable the DMA transmission */
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ETHERNET_MAC->OMR &= ~EMAC_DMAOMR_ST;
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}
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}
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/**
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* Enables or disables the DMA reception.
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*/
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void EMAC_DMAReceptionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
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{
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if (NewState)
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{
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/* Enable the DMA reception */
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ETHERNET_MAC->OMR |= EMAC_DMAOMR_SR;
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}
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else
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{
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/* Disable the DMA reception */
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ETHERNET_MAC->OMR &= ~EMAC_DMAOMR_SR;
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}
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}
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/**
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* Enables ENET MAC and DMA reception/transmission
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*/
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void EMAC_start(struct rt_synopsys_eth * ETHERNET_MAC)
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{
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/* Enable transmit state machine of the MAC for transmission on the MII */
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EMAC_MACTransmissionCmd(ETHERNET_MAC, RT_TRUE);
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/* Flush Transmit FIFO */
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enet_txfifo_flush();
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/* Enable receive state machine of the MAC for reception from the MII */
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EMAC_MACReceptionCmd(ETHERNET_MAC, RT_TRUE);
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/* Start DMA transmission */
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EMAC_DMATransmissionCmd(ETHERNET_MAC, RT_TRUE);
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/* Start DMA reception */
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EMAC_DMAReceptionCmd(ETHERNET_MAC, RT_TRUE);
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}
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/**
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* Clears the ETHERNET's DMA interrupt pending bit.
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*/
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void EMAC_clear_pending(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t pending)
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{
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/* Clear the selected ETHERNET DMA IT */
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ETHERNET_MAC->SR = (rt_uint32_t) pending;
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}
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/**
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* Resumes the DMA Transmission by writing to the DmaRxPollDemand register
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* (the data written could be anything). This forces the DMA to resume reception.
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*/
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void EMAC_resume_reception(struct rt_synopsys_eth * ETHERNET_MAC)
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{
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ETHERNET_MAC->RPDR = 0;
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}
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/**
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* Resumes the DMA Transmission by writing to the DmaTxPollDemand register
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* (the data written could be anything). This forces the DMA to resume transmission.
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*/
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void EMAC_resume_transmission(struct rt_synopsys_eth * ETHERNET_MAC)
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{
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ETHERNET_MAC->TPDR = 0;
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}
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/**
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* Read a PHY register
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*/
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rt_uint16_t EMAC_PHY_read(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint16_t PHYAddress, rt_uint16_t PHYReg)
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{
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rt_uint32_t value = 0;
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volatile rt_uint32_t timeout = 0;
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/* Get the ETHERNET MACMIIAR value */
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value = ETHERNET_MAC->GAR;
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/* Keep only the CSR Clock Range CR[2:0] bits value */
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value &= ~MACMIIAR_CR_MASK;
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/* Prepare the MII address register value */
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value |=(((rt_uint32_t)PHYAddress<<11) & EMAC_MACMIIAR_PA); /* Set the PHY device address */
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value |=(((rt_uint32_t)PHYReg<<6) & EMAC_MACMIIAR_MR); /* Set the PHY register address */
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value &= ~EMAC_MACMIIAR_MW; /* Set the read mode */
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value |= EMAC_MACMIIAR_MB; /* Set the MII Busy bit */
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/* Write the result value into the MII Address register */
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ETHERNET_MAC->GAR = value;
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/* Check for the Busy flag */
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do
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{
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timeout++;
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value = ETHERNET_MAC->GAR;
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}
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while ((value & EMAC_MACMIIAR_MB) && (timeout < (rt_uint32_t)PHY_READ_TO));
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/* Return ERROR in case of timeout */
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if(timeout == PHY_READ_TO)
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{
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return (rt_uint16_t)EMAC_ERROR;
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}
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/* Return data register value */
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return (rt_uint16_t)(ETHERNET_MAC->GDR);
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}
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/**
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* Write to a PHY register
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*/
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rt_uint32_t EMAC_PHY_write(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint16_t PHYAddress, rt_uint16_t PHYReg, rt_uint16_t PHYValue)
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{
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rt_uint32_t value = 0;
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volatile rt_uint32_t timeout = 0;
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/* Get the ETHERNET MACMIIAR value */
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value = ETHERNET_MAC->GAR;
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/* Keep only the CSR Clock Range CR[2:0] bits value */
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value &= ~MACMIIAR_CR_MASK;
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/* Prepare the MII register address value */
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value |=(((rt_uint32_t)PHYAddress<<11) & EMAC_MACMIIAR_PA); /* Set the PHY device address */
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value |=(((rt_uint32_t)PHYReg<<6) & EMAC_MACMIIAR_MR); /* Set the PHY register address */
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value |= EMAC_MACMIIAR_MW; /* Set the write mode */
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value |= EMAC_MACMIIAR_MB; /* Set the MII Busy bit */
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/* Give the value to the MII data register */
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ETHERNET_MAC->GDR = PHYValue;
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/* Write the result value into the MII Address register */
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ETHERNET_MAC->GAR = value;
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/* Check for the Busy flag */
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do
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{
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timeout++;
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value = ETHERNET_MAC->GAR;
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}
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while ((value & EMAC_MACMIIAR_MB) && (timeout < (rt_uint32_t)PHY_WRITE_TO));
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/* Return ERROR in case of timeout */
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if(timeout == PHY_WRITE_TO)
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{
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return EMAC_ERROR;
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}
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/* Return SUCCESS */
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return EMAC_SUCCESS;
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}
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