149 lines
3.6 KiB
C
149 lines
3.6 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-06 Bernard first version
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* 2014-04-03 Grissiom port to VMM
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <irq_numbers.h>
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#include <interrupt.h>
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#include <gic.h>
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#include "cp15.h"
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#define MAX_HANDLERS IMX_INTERRUPT_COUNT
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extern volatile rt_uint8_t rt_interrupt_nest;
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/* exception and interrupt handler table */
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struct rt_irq_desc isr_table[MAX_HANDLERS];
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rt_uint32_t rt_interrupt_from_thread;
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rt_uint32_t rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrupt_flag;
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extern void rt_cpu_vector_set_base(unsigned int addr);
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extern int system_vectors;
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/* keep compatible with platform SDK */
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void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr)
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{
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rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, NULL, "unknown");
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}
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void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority)
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{
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gic_set_irq_priority(irq_id, priority);
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gic_set_irq_security(irq_id, false); // set IRQ as non-secure
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gic_set_cpu_target(irq_id, cpu_id, true);
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gic_enable_irq(irq_id, true);
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}
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void disable_interrupt(uint32_t irq_id, uint32_t cpu_id)
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{
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gic_enable_irq(irq_id, false);
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gic_set_cpu_target(irq_id, cpu_id, false);
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}
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static void rt_hw_vector_init(void)
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{
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int sctrl;
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unsigned int *src = (unsigned int *)&system_vectors;
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/* C12-C0 is only active when SCTLR.V = 0 */
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asm volatile ("mrc p15, #0, %0, c1, c0, #0"
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:"=r" (sctrl));
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sctrl &= ~(1 << 13);
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asm volatile ("mcr p15, #0, %0, c1, c0, #0"
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:
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:"r" (sctrl));
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asm volatile ("mcr p15, #0, %0, c12, c0, #0"
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:
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:"r" (src));
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}
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/**
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* This function will initialize hardware interrupt
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*/
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void rt_hw_interrupt_init(void)
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{
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rt_hw_vector_init();
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gic_init();
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/* init interrupt nest, and context in thread sp */
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rt_interrupt_nest = 0;
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rt_interrupt_from_thread = 0;
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rt_interrupt_to_thread = 0;
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rt_thread_switch_interrupt_flag = 0;
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}
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/**
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* This function will mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_mask(int vector)
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{
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disable_interrupt(vector, 0);
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}
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/**
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* This function will un-mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_umask(int vector)
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{
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enable_interrupt(vector, 0, 0);
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}
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/**
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* This function will install a interrupt service routine to a interrupt.
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* @param vector the interrupt number
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* @param new_handler the interrupt service routine to be installed
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* @param old_handler the old interrupt service routine
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*/
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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void *param, const char *name)
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{
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rt_isr_handler_t old_handler = RT_NULL;
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if (vector < MAX_HANDLERS)
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{
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old_handler = isr_table[vector].handler;
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if (handler != RT_NULL)
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{
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#ifdef RT_USING_INTERRUPT_INFO
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rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
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#endif /* RT_USING_INTERRUPT_INFO */
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isr_table[vector].handler = handler;
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isr_table[vector].param = param;
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}
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// arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id());
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}
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return old_handler;
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}
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/**
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* Trigger a software IRQ
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*
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* Since we are running in single core, the target CPU are always CPU0.
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*/
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void rt_hw_interrupt_trigger(int vector)
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{
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// arm_gic_trigger(0, 1, vector);
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}
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void rt_hw_interrupt_clear(int vector)
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{
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gic_write_end_of_irq(vector);
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}
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