146 lines
4.8 KiB
C
146 lines
4.8 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-12-04 Jiaxun Yang Initial version
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*/
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#ifndef _MIPS_PTRACE_H
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#define _MIPS_PTRACE_H
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#include "asm.h"
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#include "mips_regs.h"
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#define HI_LO_SIZE 4
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#define FP_REG_SIZE 8
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#define NUM_FPU_REGS 16
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#ifndef __ASSEMBLY__
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#include <rtthread.h>
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struct mips_fpu_struct {
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rt_uint64_t fpr[NUM_FPU_REGS];
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rt_uint32_t fcr31;
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rt_uint32_t pad;
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};
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struct pt_regs {
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#ifndef ARCH_MIPS64
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/* Only O32 Need This! */
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/* Pad bytes for argument save space on the stack. */
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rt_uint32_t pad0[8];
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/* Saved main processor registers. */
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rt_uint32_t regs[32];
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/* Saved special registers. */
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rt_uint32_t cp0_status;
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rt_uint32_t hi;
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rt_uint32_t lo;
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rt_uint32_t cp0_badvaddr;
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rt_uint32_t cp0_cause;
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rt_uint32_t cp0_epc;
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#else
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/* Saved main processor registers. */
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unsigned long regs[32];
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/* Saved special registers. */
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rt_uint32_t cp0_status;
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rt_uint32_t hi;
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rt_uint32_t lo;
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unsigned long cp0_badvaddr;
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rt_uint32_t cp0_cause;
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unsigned long cp0_epc;
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#endif
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#ifdef RT_USING_FPU
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/* FPU Registers */
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/* Unlike Linux Kernel, we save these registers unconditionally,
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* so it should be a part of pt_regs */
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struct mips_fpu_struct fpu;
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#endif
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} __attribute__((aligned(8)));
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#endif
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/* Note: For call stack o32 ABI has 0x8 shadowsoace Here */
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#ifdef ARCH_MIPS64
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#define PT_R0 (0x0 * LONGSIZE) /* 0 */
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#else
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#define PT_R0 (0x8 * LONGSIZE) /* 0 */
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#endif
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#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */
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#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */
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#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */
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#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */
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#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */
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#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */
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#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */
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#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */
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#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */
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#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */
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#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */
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#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */
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#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */
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#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */
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#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */
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#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */
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#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */
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#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */
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#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */
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#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */
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#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */
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#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */
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#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */
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#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */
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#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */
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#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */
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#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */
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#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */
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#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */
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#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */
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#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */
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/*
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* Saved special registers
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*/
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#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */
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#define PT_HI ((PT_STATUS) + HI_LO_SIZE) /* 33 */
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#define PT_LO ((PT_HI) + HI_LO_SIZE) /* 34 */
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#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */
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#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */
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#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */
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#define PT_REG_END ((PT_EPC) + LONGSIZE) /* Align already ensured manually */
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#ifdef RT_USING_FPU
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#define PT_FPU_R0 (PT_REG_END)
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#define PT_FPU_R2 ((PT_FPU_R0) + FP_REG_SIZE)
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#define PT_FPU_R4 ((PT_FPU_R2) + FP_REG_SIZE)
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#define PT_FPU_R6 ((PT_FPU_R4) + FP_REG_SIZE)
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#define PT_FPU_R8 ((PT_FPU_R6) + FP_REG_SIZE)
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#define PT_FPU_R10 ((PT_FPU_R8) + FP_REG_SIZE)
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#define PT_FPU_R12 ((PT_FPU_R10) + FP_REG_SIZE)
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#define PT_FPU_R14 ((PT_FPU_R12) + FP_REG_SIZE)
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#define PT_FPU_R16 ((PT_FPU_R14) + FP_REG_SIZE)
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#define PT_FPU_R18 ((PT_FPU_R16) + FP_REG_SIZE)
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#define PT_FPU_R20 ((PT_FPU_R18) + FP_REG_SIZE)
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#define PT_FPU_R22 ((PT_FPU_R20) + FP_REG_SIZE)
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#define PT_FPU_R24 ((PT_FPU_R22) + FP_REG_SIZE)
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#define PT_FPU_R26 ((PT_FPU_R24) + FP_REG_SIZE)
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#define PT_FPU_R28 ((PT_FPU_R26) + FP_REG_SIZE)
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#define PT_FPU_R30 ((PT_FPU_R28) + FP_REG_SIZE)
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#define PT_FPU_FCSR31 ((PT_FPU_R30) + FP_REG_SIZE)
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#define PT_FPU_PAD0 ((PT_FPU_FCSR31) + 4)
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#define PT_FPU_END ((PT_FPU_PAD0) + 4)
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#define PT_SIZE PT_FPU_END
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#else
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#define PT_SIZE PT_REG_END
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#endif
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#endif
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