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mirror of https://github.com/RT-Thread/rt-thread.git synced 2025-02-24 00:28:53 +08:00
Chasel 94952b18fc
[bsp][mm32f526x] 1.add mm32f526x bsp; (#9940)
[bsp][mm32f526x] 1.add a bsp for mm32f526x;
2025-02-03 23:29:27 +08:00

115 lines
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x008000000
#define __ROM_SIZE 0x000040000
/*---------------------------- ITCM Configuration -----------------------------
; <h> ITCM Configuration
; <o0> ITCM Base Address <0x0-0xFFFFFFFF:8>
; <o1> ITCM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ITCM_BASE 0x00000000
#define __ITCM_SIZE 0x00008000
/*---------------------------- DTCM Configuration -----------------------------
; <h> DTCM Configuration
; <o0> DTCM Base Address <0x0-0xFFFFFFFF:8>
; <o1> DTCM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __DTCM_BASE 0x20000000
#define __DTCM_SIZE 0x00008000
/*--------------------- Embedded RAM1 Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM1 Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM1 Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM1_BASE 0x30000000
#define __RAM1_SIZE 0x0001C000
/*--------------------- Embedded RAM2 Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM2 Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM2 Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM2_BASE 0x3001C000
#define __RAM2_SIZE 0x00004000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000800
#define __HEAP_SIZE 0x00000C00
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM1_BASE + __RAM1_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
; *(Veneer$$CMSE) ; uncomment for secure applications
.ANY (+RO)
.ANY (+XO)
}
RW_ITCM __ITCM_BASE __ITCM_SIZE { ; RW data
.ANY (+RW +ZI)
}
RW_DTCM __DTCM_BASE __DTCM_SIZE { ; RW data
.ANY (+RW +ZI)
}
RW_RAM1 __RAM1_BASE (__RAM1_SIZE - __STACK_SIZE - __HEAP_SIZE) { ; RW data
.ANY (+RW +ZI)
}
RW_RAM2 __RAM2_BASE __RAM2_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}