375 lines
9.2 KiB
C
375 lines
9.2 KiB
C
/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2011-09-15 Bernard first version
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* 2019-07-28 zdzn add smp support
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <board.h>
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#include "cp15.h"
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#define DBG_TAG "libcpu.aarch64.cpu"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#include <string.h>
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#include "cpu.h"
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#include "psci_api.h"
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void (*system_off)(void);
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#ifdef RT_USING_SMP
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#ifdef RT_USING_FDT
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#include "dtb_node.h"
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struct dtb_node *_cpu_node[RT_CPUS_NR];
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#endif /* RT_USING_FDT */
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#define MPIDR_AFF_MASK 0x000000FF00FFFFFFul
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#define REPORT_ERR(retval) LOG_E("got error code %d in %s(), %s:%d", (retval), __func__, __FILE__, __LINE__)
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#define CHECK_RETVAL(retval) if (retval) {REPORT_ERR(retval);}
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/**
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* cpu_ops_tbl contains cpu_ops_t for each cpu kernel observed,
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* given cpu logical id 'i', its cpu_ops_t is 'cpu_ops_tbl[i]'
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*/
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struct cpu_ops_t *cpu_ops_tbl[RT_CPUS_NR];
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#ifdef RT_USING_SMART
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// _id_to_mpidr is a table translate logical id to mpid, which is a 64-bit value
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rt_uint64_t rt_cpu_mpidr_early[RT_CPUS_NR] rt_weak = {[0 ... RT_CPUS_NR - 1] = ID_ERROR};
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#else
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/* The more common mpidr_el1 table, redefine it in BSP if it is in other cases */
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rt_weak rt_uint64_t rt_cpu_mpidr_early[] =
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{
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[0] = 0x80000000,
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[1] = 0x80000001,
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[2] = 0x80000002,
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[3] = 0x80000003,
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[4] = 0x80000004,
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[5] = 0x80000005,
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[6] = 0x80000006,
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[7] = 0x80000007,
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[RT_CPUS_NR] = 0
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};
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#endif /* RT_USING_SMART */
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void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
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{
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lock->slock = 0;
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}
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#define TICKET_SHIFT 16
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void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
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{
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unsigned int tmp;
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struct __arch_tickets lockval, newval;
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asm volatile(
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/* Atomically increment the next ticket. */
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" prfm pstl1strm, %3\n"
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"1: ldaxr %w0, %3\n"
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" add %w1, %w0, %w5\n"
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" stxr %w2, %w1, %3\n"
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" cbnz %w2, 1b\n"
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/* Did we get the lock? */
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" eor %w1, %w0, %w0, ror #16\n"
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" cbz %w1, 3f\n"
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/*
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* No: spin on the owner. Send a local event to avoid missing an
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* unlock before the exclusive load.
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*/
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" sevl\n"
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"2: wfe\n"
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" ldaxrh %w2, %4\n"
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" eor %w1, %w2, %w0, lsr #16\n"
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" cbnz %w1, 2b\n"
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/* We got the lock. Critical section starts here. */
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"3:"
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: "=&r"(lockval), "=&r"(newval), "=&r"(tmp), "+Q"(*lock)
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: "Q"(lock->tickets.owner), "I"(1 << TICKET_SHIFT)
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: "memory");
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rt_hw_dmb();
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}
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void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
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{
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rt_hw_dmb();
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asm volatile(
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" stlrh %w1, %0\n"
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: "=Q"(lock->tickets.owner)
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: "r"(lock->tickets.owner + 1)
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: "memory");
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}
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static int _cpus_init_data_hardcoded(int num_cpus, rt_uint64_t *cpu_hw_ids, struct cpu_ops_t *cpu_ops[])
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{
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// load in cpu_hw_ids in cpuid_to_hwid,
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// cpu_ops to cpu_ops_tbl
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if (num_cpus > RT_CPUS_NR)
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{
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LOG_W("num_cpus (%d) greater than RT_CPUS_NR (%d)\n", num_cpus, RT_CPUS_NR);
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num_cpus = RT_CPUS_NR;
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}
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for (int i = 0; i < num_cpus; i++)
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{
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set_hwid(i, cpu_hw_ids[i]);
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cpu_ops_tbl[i] = cpu_ops[i];
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}
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return 0;
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}
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#ifdef RT_USING_FDT
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/** read ('size' * 4) bytes number from start, big-endian format */
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static rt_uint64_t _read_be_number(void *start, int size)
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{
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rt_uint64_t buf = 0;
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for (; size > 0; size--)
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buf = (buf << 32) | fdt32_to_cpu(*(uint32_t *)start++);
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return buf;
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}
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/** check device-type of the node, */
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static bool _node_is_cpu(struct dtb_node *node)
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{
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char *device_type = dtb_node_get_dtb_node_property_value(node, "device_type", NULL);
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if (device_type)
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{
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return !strcmp(device_type, "cpu");
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}
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return false;
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}
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static int _read_and_set_hwid(struct dtb_node *cpu, int *id_pool, int *pcpuid)
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{
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// size/address_cells is number of elements in reg array
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int size;
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static int address_cells, size_cells;
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if (!address_cells && !size_cells)
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dtb_node_get_dtb_node_cells(cpu, &address_cells, &size_cells);
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void *id_start = dtb_node_get_dtb_node_property_value(cpu, "reg", &size);
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rt_uint64_t mpid = _read_be_number(id_start, address_cells);
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*pcpuid = *id_pool;
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*id_pool = *id_pool + 1;
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set_hwid(*pcpuid, mpid);
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LOG_I("Using MPID 0x%lx as cpu %d", mpid, *pcpuid);
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// setting _cpu_node for cpu_init use
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_cpu_node[*pcpuid] = cpu;
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return 0;
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}
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static int _read_and_set_cpuops(struct dtb_node *cpu, int cpuid)
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{
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char *method = dtb_node_get_dtb_node_property_value(cpu, "enable-method", NULL);
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if (!method)
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{
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LOG_E("Cannot read method from cpu node");
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return -1;
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}
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struct cpu_ops_t *cpu_ops;
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if (!strcmp(method, cpu_ops_psci.method))
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{
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cpu_ops = &cpu_ops_psci;
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}
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else if (!strcmp(method, cpu_ops_spin_tbl.method))
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{
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cpu_ops = &cpu_ops_spin_tbl;
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}
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else
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{
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cpu_ops = RT_NULL;
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LOG_E("Not supported cpu_ops: %s", method);
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}
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cpu_ops_tbl[cpuid] = cpu_ops;
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LOG_D("Using boot method [%s] for cpu %d", cpu_ops->method, cpuid);
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return 0;
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}
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static int _cpus_init_data_fdt()
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{
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// cpuid_to_hwid and cpu_ops_tbl with fdt
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void *root = get_dtb_node_head();
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int id_pool = 0;
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int cpuid;
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struct dtb_node *cpus = dtb_node_get_dtb_node_by_path(root, "/cpus");
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// for each cpu node (device-type is cpu), read its mpid and set its cpuid_to_hwid
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for_each_node_child(cpus)
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{
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if (!_node_is_cpu(cpus))
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{
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continue;
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}
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if (id_pool > RT_CPUS_NR)
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{
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LOG_W("Reading more cpus from FDT than RT_CPUS_NR"
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"\n Parsing will not continue and only %d cpus will be used.", RT_CPUS_NR);
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break;
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}
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_read_and_set_hwid(cpus, &id_pool, &cpuid);
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_read_and_set_cpuops(cpus, cpuid);
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}
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return 0;
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}
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#endif /* RT_USING_FDT */
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/** init cpu with hardcoded infomation or parsing from FDT */
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static int _cpus_init(int num_cpus, rt_uint64_t *cpu_hw_ids, struct cpu_ops_t *cpu_ops[])
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{
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int retval;
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// first setup cpu_ops_tbl and cpuid_to_hwid
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if (num_cpus > 0)
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retval = _cpus_init_data_hardcoded(num_cpus, cpu_hw_ids, cpu_ops);
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else
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{
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retval = -1;
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#ifdef RT_USING_FDT
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retval = _cpus_init_data_fdt();
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#endif
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}
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if (retval)
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return retval;
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// using cpuid_to_hwid and cpu_ops_tbl to call method_init and cpu_init
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// assuming that cpuid 0 has already init
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for (int i = 1; i < RT_CPUS_NR; i++)
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{
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if (cpuid_to_hwid(i) == ID_ERROR)
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{
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LOG_E("Failed to find hardware id of CPU %d", i);
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continue;
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}
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if (cpu_ops_tbl[i] && cpu_ops_tbl[i]->cpu_init)
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{
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retval = cpu_ops_tbl[i]->cpu_init(i);
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CHECK_RETVAL(retval);
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}
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else
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{
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LOG_E("Failed to find cpu_init for cpu %d with cpu_ops[%p], cpu_ops->cpu_init[%p]"
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, cpuid_to_hwid(i), cpu_ops_tbl[i], cpu_ops_tbl[i] ? cpu_ops_tbl[i]->cpu_init : NULL);
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}
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}
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return 0;
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}
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static void _boot_secondary(void)
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{
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for (int i = 1; i < RT_CPUS_NR; i++)
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{
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int retval = -0xbad0; // mark no support operation
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if (cpu_ops_tbl[i] && cpu_ops_tbl[i]->cpu_boot)
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retval = cpu_ops_tbl[i]->cpu_boot(i);
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if (retval)
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{
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if (retval == -0xbad0)
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LOG_E("No cpu_ops was probed for CPU %d. Try to configure it or use fdt", i);
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else
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LOG_E("Failed to boot secondary CPU %d, error code %d", i, retval);
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} else {
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LOG_I("Secondary CPU %d booted", i);
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}
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}
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}
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rt_weak void rt_hw_secondary_cpu_up(void)
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{
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_boot_secondary();
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}
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/**
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* @brief boot cpu with hardcoded data
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*
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* @param num_cpus number of cpus
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* @param cpu_hw_ids each element represents a hwid of cpu[i]
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* @param cpu_ops each element represents a pointer to cpu_ops of cpu[i]
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* @return int 0 on success,
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*/
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int rt_hw_cpu_boot_secondary(int num_cpus, rt_uint64_t *cpu_hw_ids, struct cpu_ops_t *cpu_ops[])
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{
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int retval = 0;
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if (num_cpus < 1 || !cpu_hw_ids || !cpu_ops)
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return -1;
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retval = _cpus_init(num_cpus, cpu_hw_ids, cpu_ops);
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CHECK_RETVAL(retval);
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return retval;
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}
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#define CPU_INIT_USING_FDT 0,0,0
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/**
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* @brief Initialize cpu infomation from fdt
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*
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* @return int
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*/
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int rt_hw_cpu_init()
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{
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#ifdef RT_USING_FDT
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return _cpus_init(CPU_INIT_USING_FDT);
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#else
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LOG_E("CPU init failed since RT_USING_FDT was not defined");
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return -0xa; /* no fdt support */
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#endif /* RT_USING_FDT */
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}
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rt_weak void rt_hw_secondary_cpu_idle_exec(void)
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{
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asm volatile("wfe" ::
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: "memory", "cc");
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}
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#endif /*RT_USING_SMP*/
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/**
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* @addtogroup ARM CPU
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*/
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/*@{*/
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const char *rt_hw_cpu_arch(void)
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{
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return "aarch64";
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}
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/** shutdown CPU */
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rt_weak void rt_hw_cpu_shutdown()
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{
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rt_uint32_t level;
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rt_kprintf("shutdown...\n");
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if (system_off)
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system_off();
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LOG_E("system shutdown failed");
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level = rt_hw_interrupt_disable();
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while (level)
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{
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RT_ASSERT(0);
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}
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}
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MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_shutdown, shutdown, shutdown machine);
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/*@}*/
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