358 lines
21 KiB
C
358 lines
21 KiB
C
/*
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* @brief EMC Registers and control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __EMC_001_H_
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#define __EMC_001_H_
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#include "sys_config.h"
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup IP_EMC_001 IP: EMC register block and driver
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* @ingroup IP_Drivers
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* External Memory Controller
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* @{
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*/
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/**
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* @brief External Memory Controller (EMC) register block structure
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*/
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typedef struct { /*!< EMC Structure */
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__IO uint32_t CONTROL; /*!< Controls operation of the memory controller. */
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__I uint32_t STATUS; /*!< Provides EMC status information. */
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__IO uint32_t CONFIG; /*!< Configures operation of the memory controller. */
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__I uint32_t RESERVED0[5];
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__IO uint32_t DYNAMICCONTROL; /*!< Controls dynamic memory operation. */
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__IO uint32_t DYNAMICREFRESH; /*!< Configures dynamic memory refresh operation. */
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__IO uint32_t DYNAMICREADCONFIG; /*!< Configures the dynamic memory read strategy. */
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__I uint32_t RESERVED1;
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__IO uint32_t DYNAMICRP; /*!< Selects the precharge command period. */
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__IO uint32_t DYNAMICRAS; /*!< Selects the active to precharge command period. */
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__IO uint32_t DYNAMICSREX; /*!< Selects the self-refresh exit time. */
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__IO uint32_t DYNAMICAPR; /*!< Selects the last-data-out to active command time. */
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__IO uint32_t DYNAMICDAL; /*!< Selects the data-in to active command time. */
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__IO uint32_t DYNAMICWR; /*!< Selects the write recovery time. */
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__IO uint32_t DYNAMICRC; /*!< Selects the active to active command period. */
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__IO uint32_t DYNAMICRFC; /*!< Selects the auto-refresh period. */
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__IO uint32_t DYNAMICXSR; /*!< Selects the exit self-refresh to active command time. */
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__IO uint32_t DYNAMICRRD; /*!< Selects the active bank A to active bank B latency. */
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__IO uint32_t DYNAMICMRD; /*!< Selects the load mode register to active command time. */
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__I uint32_t RESERVED2[9];
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__IO uint32_t STATICEXTENDEDWAIT; /*!< Selects time for long static memory read and write transfers. */
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__I uint32_t RESERVED3[31];
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__IO uint32_t DYNAMICCONFIG0; /*!< Selects the configuration information for dynamic memory chip select n. */
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__IO uint32_t DYNAMICRASCAS0; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
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__I uint32_t RESERVED4[6];
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__IO uint32_t DYNAMICCONFIG1; /*!< Selects the configuration information for dynamic memory chip select n. */
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__IO uint32_t DYNAMICRASCAS1; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
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__I uint32_t RESERVED5[6];
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__IO uint32_t DYNAMICCONFIG2; /*!< Selects the configuration information for dynamic memory chip select n. */
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__IO uint32_t DYNAMICRASCAS2; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
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__I uint32_t RESERVED6[6];
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__IO uint32_t DYNAMICCONFIG3; /*!< Selects the configuration information for dynamic memory chip select n. */
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__IO uint32_t DYNAMICRASCAS3; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
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__I uint32_t RESERVED7[38];
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__IO uint32_t STATICCONFIG0; /*!< Selects the memory configuration for static chip select n. */
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__IO uint32_t STATICWAITWEN0; /*!< Selects the delay from chip select n to write enable. */
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__IO uint32_t STATICWAITOEN0; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
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__IO uint32_t STATICWAITRD0; /*!< Selects the delay from chip select n to a read access. */
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__IO uint32_t STATICWAITPAG0; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
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__IO uint32_t STATICWAITWR0; /*!< Selects the delay from chip select n to a write access. */
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__IO uint32_t STATICWAITTURN0; /*!< Selects bus turnaround cycles */
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__I uint32_t RESERVED8;
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__IO uint32_t STATICCONFIG1; /*!< Selects the memory configuration for static chip select n. */
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__IO uint32_t STATICWAITWEN1; /*!< Selects the delay from chip select n to write enable. */
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__IO uint32_t STATICWAITOEN1; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
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__IO uint32_t STATICWAITRD1; /*!< Selects the delay from chip select n to a read access. */
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__IO uint32_t STATICWAITPAG1; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
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__IO uint32_t STATICWAITWR1; /*!< Selects the delay from chip select n to a write access. */
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__IO uint32_t STATICWAITTURN1; /*!< Selects bus turnaround cycles */
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__I uint32_t RESERVED9;
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__IO uint32_t STATICCONFIG2; /*!< Selects the memory configuration for static chip select n. */
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__IO uint32_t STATICWAITWEN2; /*!< Selects the delay from chip select n to write enable. */
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__IO uint32_t STATICWAITOEN2; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
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__IO uint32_t STATICWAITRD2; /*!< Selects the delay from chip select n to a read access. */
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__IO uint32_t STATICWAITPAG2; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
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__IO uint32_t STATICWAITWR2; /*!< Selects the delay from chip select n to a write access. */
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__IO uint32_t STATICWAITTURN2; /*!< Selects bus turnaround cycles */
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__I uint32_t RESERVED10;
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__IO uint32_t STATICCONFIG3; /*!< Selects the memory configuration for static chip select n. */
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__IO uint32_t STATICWAITWEN3; /*!< Selects the delay from chip select n to write enable. */
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__IO uint32_t STATICWAITOEN3; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
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__IO uint32_t STATICWAITRD3; /*!< Selects the delay from chip select n to a read access. */
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__IO uint32_t STATICWAITPAG3; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
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__IO uint32_t STATICWAITWR3; /*!< Selects the delay from chip select n to a write access. */
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__IO uint32_t STATICWAITTURN3; /*!< Selects bus turnaround cycles */
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} IP_EMC_001_Type;
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/**
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* @brief EMC register support bitfields and mask
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*/
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/* Reserve for extending support to ARM9 or nextgen LPC */
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#define EMC_SUPPORT_ONLY_PL172 /*!< Reserve for extending support to ARM9 or nextgen LPC */
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#define EMC_CONFIG_ENDIAN_LITTLE (0) /*!< Value for EMC to operate in Little Endian Mode */
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#define EMC_CONFIG_ENDIAN_BIG (1) /*!< Value for EMC to operate in Big Endian Mode */
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#define EMC_CONFIG_BUFFER_ENABLE (1 << 19) /*!< EMC Buffer enable bit in EMC Dynamic Configuration register */
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#define EMC_CONFIG_WRITE_PROTECT (1 << 20) /*!< EMC Write protect bit in EMC Dynamic Configuration register */
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/* Dynamic Memory Configuration Register Bit Definitions */
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#define EMC_DYN_CONFIG_MD_BIT (3) /*!< Memory device bit in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_MD_SDRAM (0 << EMC_DYN_CONFIG_MD_BIT) /*!< Select device as SDRAM in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_MD_LPSDRAM (1 << EMC_DYN_CONFIG_MD_BIT) /*!< Select device as LPSDRAM in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_LPSDRAM_BIT (12) /*!< LPSDRAM bit in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_LPSDRAM (1 << EMC_DYN_CONFIG_LPSDRAM_BIT) /*!< LPSDRAM value in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_DEV_SIZE_BIT (9) /*!< Device Size starting bit in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_DEV_SIZE_16Mb (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 16Mb Device Size value in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_DEV_SIZE_64Mb (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 64Mb Device Size value in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_DEV_SIZE_128Mb (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 128Mb Device Size value in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_DEV_SIZE_256Mb (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 256Mb Device Size value in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_DEV_SIZE_512Mb (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 512Mb Device Size value in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_DEV_BUS_BIT (7) /*!< Device bus width starting bit in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_DEV_BUS_8 (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 8-bit bus width value in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_DEV_BUS_16 (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 16-bit bus width value in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_DEV_BUS_32 (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 32-bit bus width value in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT (14) /*!< Device data bus width starting bit in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_DATA_BUS_16 (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT) /*!< Device 16-bit data bus width value in EMC Dynamic Configuration register */
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#define EMC_DYN_CONFIG_DATA_BUS_32 (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT) /*!< Device 32-bit bus width value in EMC Dynamic Configuration register */
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/*!< Memory configuration values in EMC Dynamic Configuration Register */
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#define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS ((0x0 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 2Mx8 2 Banks 11 Rows 9 Columns */
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#define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS ((0x0 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 1Mx16 2 Banks 11 Rows 8 Columns */
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#define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS ((0x1 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 8Mx8 4 Banks 12 Rows 9 Columns */
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#define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS ((0x1 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 4Mx16 4 Banks 12 Rows 8 Columns */
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#define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS ((0x1 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 2Mx32 4 Banks 11 Rows 8 Columns */
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#define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS ((0x2 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 16Mx8 4 Banks 12 Rows 10 Columns */
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#define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 8Mx16 4 Banks 12 Rows 9 Columns */
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#define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS ((0x2 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 4Mx32 4 Banks 12 Rows 8 Columns */
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#define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS ((0x3 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 32Mx8 4 Banks 13 Rows 10 Columns */
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#define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 16Mx16 4 Banks 13 Rows 8 Columns */
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#define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS ((0x3 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 8Mx32 4 Banks 13 Rows 8 Columns */
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#define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS ((0x4 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 64Mx8 4 Banks 13 Rows 11 Columns */
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#define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 32Mx16 4 Banks 13 Rows 10 Columns */
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/*!< Dynamic Memory Mode Register Bit Definition */
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#define EMC_DYN_MODE_BURST_LEN_BIT (0) /*!< Starting bit No. of Burst Length in Dynamic Memory Mode Register */
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#define EMC_DYN_MODE_BURST_LEN_1 (0) /*!< Value to set Burst Length to 1 in Dynamic Memory Mode Register */
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#define EMC_DYN_MODE_BURST_LEN_2 (1) /*!< Value to set Burst Length to 2 in Dynamic Memory Mode Register */
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#define EMC_DYN_MODE_BURST_LEN_4 (2) /*!< Value to set Burst Length to 4 in Dynamic Memory Mode Register */
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#define EMC_DYN_MODE_BURST_LEN_8 (3) /*!< Value to set Burst Length to 8 in Dynamic Memory Mode Register */
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#define EMC_DYN_MODE_BURST_LEN_FULL (7) /*!< Value to set Burst Length to Full in Dynamic Memory Mode Register */
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#define EMC_DYN_MODE_BURST_TYPE_BIT (3) /*!< Burst Type bit in Dynamic Memory Mode Register */
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#define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL (0 << EMC_DYN_MODE_BURST_TYPE_BIT) /*!< Burst Type Sequential in Dynamic Memory Mode Register */
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#define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE (1 << EMC_DYN_MODE_BURST_TYPE_BIT) /*!< Burst Type Interleaved in Dynamic Memory Mode Register */
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/*!< CAS Latency in Dynamic Mode Register */
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#define EMC_DYN_MODE_CAS_BIT (4) /*!< CAS latency starting bit in Dynamic Memory Mode register */
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#define EMC_DYN_MODE_CAS_1 (1 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 1 cycle */
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#define EMC_DYN_MODE_CAS_2 (2 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 2 cycle */
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#define EMC_DYN_MODE_CAS_3 (3 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 3 cycle */
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/*!< Operation Mode in Dynamic Mode register */
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#define EMC_DYN_MODE_OPMODE_BIT (7) /*!< Dynamic Mode Operation bit */
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#define EMC_DYN_MODE_OPMODE_STANDARD (0 << EMC_DYN_MODE_OPMODE_BIT) /*!< Value for Dynamic standard operation Mode */
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/*!< Write Burst Mode in Dynamic Mode register */
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#define EMC_DYN_MODE_WBMODE_BIT (9) /*!< Write Burst Mode bit */
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#define EMC_DYN_MODE_WBMODE_PROGRAMMED (0 << EMC_DYN_MODE_WBMODE_BIT) /*!< Write Burst Mode programmed */
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#define EMC_DYN_MODE_WBMODE_SINGLE_LOC (1 << EMC_DYN_MODE_WBMODE_BIT) /*!< Write Burst Mode Single LOC */
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/*!< Dynamic Memory Control Register Bit Definitions */
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#define EMC_DYN_CONTROL_DEEPSLEEP_BIT (13) /*!< Deep sleep Mode bit */
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#define EMC_DYN_CONTROL_ENABLE (0x03) /*!< Control Enable value */
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/*!< Static Memory Configuration Register Bit Definitions */
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#define EMC_STATIC_CONFIG_MEM_WIDTH_8 (0) /*!< Static Memory Configuration - 8-bit width */
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#define EMC_STATIC_CONFIG_MEM_WIDTH_16 (1) /*!< Static Memory Configuration - 16-bit width */
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#define EMC_STATIC_CONFIG_MEM_WIDTH_32 (2) /*!< Static Memory Configuration - 32-bit width */
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#define EMC_STATIC_CONFIG_PAGE_MODE_BIT (3) /*!< Page Mode bit No */
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#define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT) /*!< Value to enable Page Mode */
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#define EMC_STATIC_CONFIG_CS_POL_BIT (6) /*!< Chip Select bit No */
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#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH (1 << EMC_STATIC_CONFIG_CS_POL_BIT) /*!< Chip Select polarity - Active High */
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#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW (0 << EMC_STATIC_CONFIG_CS_POL_BIT) /*!< Chip Select polarity - Active Low */
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#define EMC_STATIC_CONFIG_BLS_BIT (7) /*!< BLS Configuration bit No */
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#define EMC_STATIC_CONFIG_BLS_HIGH (1 << EMC_STATIC_CONFIG_BLS_BIT) /*!< BLS High Configuration value */
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#define EMC_STATIC_CONFIG_BLS_LOW (0 << EMC_STATIC_CONFIG_BLS_BIT) /*!< BLS Low Configuration value */
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#define EMC_STATIC_CONFIG_EW_BIT (8) /*!< Ext Wait bit No */
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#define EMC_STATIC_CONFIG_EW_ENABLE (1 << EMC_STATIC_CONFIG_EW_BIT) /*!< Ext Wait Enabled value */
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#define EMC_STATIC_CONFIG_EW_DISABLE (0 << EMC_STATIC_CONFIG_EW_BIT) /*!< Ext Wait Diabled value */
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/*!< Q24.8 Fixed Point Helper */
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#define Q24_8_FP(x) ((x) * 256)
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#define EMC_NANOSECOND(x) Q24_8_FP(x)
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#define EMC_CLOCK(x) Q24_8_FP(-(x))
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/**
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* @brief EMC Dynamic Device Configuration structure used for IP drivers
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*/
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typedef struct {
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uint32_t BaseAddr; /*!< Base Address */
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uint8_t RAS; /*!< RAS value */
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uint32_t ModeRegister; /*!< Mode Register value */
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uint32_t DynConfig; /*!< Dynamic Configuration value */
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} IP_EMC_DYN_DEVICE_CONFIG_Type;
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/**
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* @brief EMC Dynamic Configure Struct
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*/
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typedef struct {
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int32_t RefreshPeriod; /*!< Refresh period */
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uint32_t ReadConfig; /*!< Clock*/
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int32_t tRP; /*!< Precharge Command Period */
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int32_t tRAS; /*!< Active to Precharge Command Period */
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int32_t tSREX; /*!< Self Refresh Exit Time */
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int32_t tAPR; /*!< Last Data Out to Active Time */
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int32_t tDAL; /*!< Data In to Active Command Time */
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int32_t tWR; /*!< Write Recovery Time */
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int32_t tRC; /*!< Active to Active Command Period */
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int32_t tRFC; /*!< Auto-refresh Period */
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int32_t tXSR; /*!< Exit Selt Refresh */
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int32_t tRRD; /*!< Active Bank A to Active Bank B Time */
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int32_t tMRD; /*!< Load Mode register command to Active Command */
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IP_EMC_DYN_DEVICE_CONFIG_Type DevConfig[4]; /*!< Device Configuration array */
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} IP_EMC_DYN_CONFIG_Type;
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/**
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* @brief EMC Static Configure Structure
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*/
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typedef struct {
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uint8_t ChipSelect; /*!< Chip select */
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uint32_t Config; /*!< Configuration value */
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int32_t WaitWen; /*!< Write Enable Wait */
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int32_t WaitOen; /*!< Output Enable Wait */
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int32_t WaitRd; /*!< Read Wait */
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int32_t WaitPage; /*!< Page Access Wait */
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int32_t WaitWr; /*!< Write Wait */
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int32_t WaitTurn; /*!< Turn around wait */
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} IP_EMC_STATIC_CONFIG_Type;
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/**
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* @brief Initializes the Dynamic Controller
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* @param pEMC : Pointer to EMC peripheral
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* @param Dynamic_Config : Dynamic Memory Configure Struct
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* @param EMC_Clock : Frequency of EMC Clock Out
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* @return None
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* Initializes the Dynamic Controller according to the specified parameters
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* in the IP_EMC_DYN_CONFIG_Type
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*/
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void IP_EMC_Dynamic_Init(IP_EMC_001_Type *pEMC, IP_EMC_DYN_CONFIG_Type *Dynamic_Config, uint32_t EMC_Clock);
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/**
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* @brief Set Deep Sleep Mode for Dynamic Memory Controller
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* @param pEMC : Pointer to EMC peripheral
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* @param Enable : 1 = enter DeepSleep Mode, 0 = Normal Mode
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* @return None
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*/
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void IP_EMC_Dynamic_DeepSleepMode(IP_EMC_001_Type *pEMC, uint32_t Enable);
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/**
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* @brief Enable Dynamic Memory Controller
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* @param pEMC : Pointer to EMC peripheral
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* @param Enable : 1 = Enable Dynamic Memory Controller, 0 = Disable
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* @return None
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*/
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void IP_EMC_Dynamic_Enable(IP_EMC_001_Type *pEMC, uint8_t Enable);
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/**
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* @brief Initializes the Static Controller according to the specified
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* parameters in the IP_EMC_STATIC_CONFIG_Type
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* @param pEMC : Pointer to EMC peripheral
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* @param Static_Config : Static Memory Configure Struct
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* @param EMC_Clock : Frequency of EMC Clock Out
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* @return None
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*/
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void IP_EMC_Static_Init(IP_EMC_001_Type *pEMC, IP_EMC_STATIC_CONFIG_Type *Static_Config, uint32_t EMC_Clock);
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/**
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* @brief Mirror CS1 to CS0 and DYCS0
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* @param pEMC : Pointer to EMC peripheral
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* @param Enable : 1 = Mirror, 0 = Normal Memory Map
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* @return None
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*/
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void IP_EMC_Mirror(IP_EMC_001_Type *pEMC, uint32_t Enable);
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/**
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* @brief Enable EMC
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* @param pEMC : Pointer to EMC peripheral
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* @param Enable : 1 = Enable, 0 = Disable
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* @return None
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*/
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void IP_EMC_Enable(IP_EMC_001_Type *pEMC, uint32_t Enable);
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/**
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* @brief Set EMC LowPower Mode
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* @param pEMC : Pointer to EMC peripheral
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* @param Enable : 1 = Enable, 0 = Disable
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* @return None
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*/
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void IP_EMC_LowPowerMode(IP_EMC_001_Type *pEMC, uint32_t Enable);
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/**
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* @brief Initialize EMC
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* @param pEMC : Pointer to EMC peripheral
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* @param Enable : 1 = Enable, 0 = Disable
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* @param ClockRatio : clock out ratio, 0 = 1:1, 1 = 1:2
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* @param EndianMode : Endian Mode, 0 = Little, 1 = Big
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* @return None
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*/
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void IP_EMC_Init(IP_EMC_001_Type *pEMC, uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode);
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/**
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* @brief Set Static Memory Extended Wait in Clock
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* @param pEMC : Pointer to EMC peripheral
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* @param Wait16Clks : Number of '16 clock' delay cycles
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* @return None
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*/
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void IP_EMC_SetStaticExtendedWait(IP_EMC_001_Type *pEMC, uint32_t Wait16Clks);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __EMC_001_H_ */
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