457 lines
17 KiB
C
457 lines
17 KiB
C
/*
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* @brief LPC5410X 32-bit Timer/PWM driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __TIMER_5410X_H_
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#define __TIMER_5410X_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup TIMER_5410X CHIP: LPC5410X 32-bit Timer driver
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* @ingroup CHIP_5410X_DRIVERS
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* @{
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*/
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/**
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* @brief 32-bit Standard timer register block structure
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*/
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typedef struct { /*!< TIMERn Structure */
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__IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
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__IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
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__IO uint32_t TC; /*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
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__IO uint32_t PR; /*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
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__IO uint32_t PC; /*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
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__IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
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__IO uint32_t MR[4]; /*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
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__IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
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__IO uint32_t CR[4]; /*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
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__IO uint32_t EMR; /*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
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__I uint32_t RESERVED0[12];
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__IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
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__IO uint32_t PWMC;
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} LPC_TIMER_T;
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/** Macro to clear interrupt pending */
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#define TIMER_IR_CLR(n) _BIT(n)
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/** Macro for getting a timer match interrupt bit */
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#define TIMER_MATCH_INT(n) (_BIT((n) & 0x0F))
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/** Macro for getting a capture event interrupt bit */
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#define TIMER_CAP_INT(n) (_BIT((((n) & 0x0F) + 4)))
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/** Timer/counter enable bit */
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#define TIMER_ENABLE ((uint32_t) (1 << 0))
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/** Timer/counter reset bit */
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#define TIMER_RESET ((uint32_t) (1 << 1))
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/** Timer Control register Mask */
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#define TIMER_CTRL_MASK ((uint32_t) 0x03)
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/** Bit location for interrupt on MRx match, n = 0 to 3 */
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#define TIMER_INT_ON_MATCH(n) (_BIT(((n) * 3)))
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/** Bit location for reset on MRx match, n = 0 to 3 */
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#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))
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/** Bit location for stop on MRx match, n = 0 to 3 */
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#define TIMER_STOP_ON_MATCH(n) (_BIT((((n) * 3) + 2)))
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/** Match Control register Mask */
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#define TIMER_MCR_MASK ((uint32_t) 0x0FFF)
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/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
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#define TIMER_CAP_RISING(n) (_BIT(((n) * 3)))
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/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
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#define TIMER_CAP_FALLING(n) (_BIT((((n) * 3) + 1)))
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/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
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#define TIMER_INT_ON_CAP(n) (_BIT((((n) * 3) + 2)))
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/** Capture Control register Mask */
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#define TIMER_CCR_MASK ((uint32_t) 0x0FFF)
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/** External Match register Mask */
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#define TIMER_EMR_MASK ((uint32_t) 0x0FFF)
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/** Counter Control register Mask */
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#define TIMER_CTCR_MASK ((uint32_t) 0x0F)
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/**
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* @brief Initialize a timer
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* @param pTMR : Pointer to timer IP register address
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* @return Nothing
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*/
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void Chip_TIMER_Init(LPC_TIMER_T *pTMR);
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/**
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* @brief Shutdown a timer
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* @param pTMR : Pointer to timer IP register address
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* @return Nothing
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*/
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void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR);
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/**
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* @brief Determine if a match interrupt is pending
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* @param pTMR : Pointer to timer IP register address
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* @param matchnum : Match interrupt number to check
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* @return false if the interrupt is not pending, otherwise true
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* @note Determine if the match interrupt for the passed timer and match
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* counter is pending.
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*/
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STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum)
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{
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return (bool) ((pTMR->IR & TIMER_MATCH_INT(matchnum)) != 0);
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}
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/**
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* @brief Determine if a capture interrupt is pending
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* @param pTMR : Pointer to timer IP register address
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* @param capnum : Capture interrupt number to check
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* @return false if the interrupt is not pending, otherwise true
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* @note Determine if the capture interrupt for the passed capture pin is
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* pending.
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*/
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STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_T *pTMR, int8_t capnum)
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{
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return (bool) ((pTMR->IR & TIMER_CAP_INT(capnum)) != 0);
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}
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/**
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* @brief Clears a (pending) match interrupt
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* @param pTMR : Pointer to timer IP register address
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* @param matchnum : Match interrupt number to clear
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* @return Nothing
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* @note Clears a pending timer match interrupt.
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*/
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STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum)
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{
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pTMR->IR = TIMER_IR_CLR(matchnum);
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}
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/**
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* @brief Clears a (pending) capture interrupt
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* @param pTMR : Pointer to timer IP register address
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* @param capnum : Capture interrupt number to clear
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* @return Nothing
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* @note Clears a pending timer capture interrupt.
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*/
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STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum)
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{
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pTMR->IR = (0x10 << capnum);
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}
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/**
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* @brief Enables the timer (starts count)
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* @param pTMR : Pointer to timer IP register address
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* @return Nothing
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* @note Enables the timer to start counting.
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*/
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STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_T *pTMR)
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{
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pTMR->TCR = (pTMR->TCR & TIMER_CTRL_MASK) | TIMER_ENABLE;
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}
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/**
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* @brief Disables the timer (stops count)
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* @param pTMR : Pointer to timer IP register address
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* @return Nothing
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* @note Disables the timer to stop counting.
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*/
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STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_T *pTMR)
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{
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pTMR->TCR = (pTMR->TCR & TIMER_CTRL_MASK) & ~TIMER_ENABLE;
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}
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/**
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* @brief Returns the current timer count
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* @param pTMR : Pointer to timer IP register address
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* @return Current timer terminal count value
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* @note Returns the current timer terminal count.
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*/
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STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_T *pTMR)
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{
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return pTMR->TC;
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}
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/**
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* @brief Returns the current prescale count
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* @param pTMR : Pointer to timer IP register address
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* @return Current timer prescale count value
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* @note Returns the current prescale count.
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*/
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STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_T *pTMR)
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{
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return pTMR->PC;
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}
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/**
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* @brief Sets the prescaler value
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* @param pTMR : Pointer to timer IP register address
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* @param prescale : Prescale value to set the prescale register to
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* @return Nothing
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* @note Sets the prescale count value.
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*/
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STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale)
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{
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pTMR->PR = prescale;
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}
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/**
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* @brief Sets a timer match value
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* @param pTMR : Pointer to timer IP register address
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* @param matchnum : Match timer to set match count for
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* @param matchval : Match value for the selected match count
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* @return Nothing
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* @note Sets one of the timer match values.
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*/
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STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval)
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{
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pTMR->MR[matchnum] = matchval;
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}
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/**
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* @brief Reads a capture register
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* @param pTMR : Pointer to timer IP register address
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* @param capnum : Capture register to read
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* @return The selected capture register value
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* @note Returns the selected capture register value.
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*/
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STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum)
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{
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return pTMR->CR[capnum];
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}
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/**
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* @brief Resets the timer terminal and prescale counts to 0
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* @param pTMR : Pointer to timer IP register address
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* @return Nothing
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*/
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void Chip_TIMER_Reset(LPC_TIMER_T *pTMR);
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/**
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* @brief Enables a match interrupt that fires when the terminal count
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* matches the match counter value.
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* @param pTMR : Pointer to timer IP register address
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* @param matchnum : Match timer, 0 to 3
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* @return Nothing
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*/
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STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
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{
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pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) | TIMER_INT_ON_MATCH(matchnum);
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}
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/**
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* @brief Disables a match interrupt for a match counter.
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* @param pTMR : Pointer to timer IP register address
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* @param matchnum : Match timer, 0 to 3
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* @return Nothing
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*/
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STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
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{
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pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) & ~TIMER_INT_ON_MATCH(matchnum);
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}
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/**
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* @brief For the specific match counter, enables reset of the terminal count register when a match occurs
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* @param pTMR : Pointer to timer IP register address
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* @param matchnum : Match timer, 0 to 3
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* @return Nothing
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*/
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STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
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{
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pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) | TIMER_RESET_ON_MATCH(matchnum);
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}
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/**
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* @brief For the specific match counter, disables reset of the terminal count register when a match occurs
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* @param pTMR : Pointer to timer IP register address
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* @param matchnum : Match timer, 0 to 3
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* @return Nothing
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*/
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STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
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{
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pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) & ~TIMER_RESET_ON_MATCH(matchnum);
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}
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/**
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* @brief Enable a match timer to stop the terminal count when a
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* match count equals the terminal count.
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* @param pTMR : Pointer to timer IP register address
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* @param matchnum : Match timer, 0 to 3
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* @return Nothing
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*/
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STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
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{
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pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) | TIMER_STOP_ON_MATCH(matchnum);
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}
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/**
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* @brief Disable stop on match for a match timer. Disables a match timer
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* to stop the terminal count when a match count equals the terminal count.
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* @param pTMR : Pointer to timer IP register address
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* @param matchnum : Match timer, 0 to 3
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* @return Nothing
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*/
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STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
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{
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pTMR->MCR = (pTMR->MCR & TIMER_MCR_MASK) & ~TIMER_STOP_ON_MATCH(matchnum);
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}
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/**
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* @brief Enables capture on on rising edge of selected CAP signal for the
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* selected capture register, enables the selected CAPn.capnum signal to load
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* the capture register with the terminal coount on a rising edge.
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* @param pTMR : Pointer to timer IP register address
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* @param capnum : Capture signal/register to use
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* @return Nothing
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*/
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STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
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{
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pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) | TIMER_CAP_RISING(capnum);
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}
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/**
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* @brief Disables capture on on rising edge of selected CAP signal. For the
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* selected capture register, disables the selected CAPn.capnum signal to load
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* the capture register with the terminal coount on a rising edge.
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* @param pTMR : Pointer to timer IP register address
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* @param capnum : Capture signal/register to use
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* @return Nothing
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*/
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STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
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{
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pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) & ~TIMER_CAP_RISING(capnum);
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}
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/**
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* @brief Enables capture on on falling edge of selected CAP signal. For the
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* selected capture register, enables the selected CAPn.capnum signal to load
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* the capture register with the terminal coount on a falling edge.
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* @param pTMR : Pointer to timer IP register address
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* @param capnum : Capture signal/register to use
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* @return Nothing
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*/
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STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
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{
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pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) | TIMER_CAP_FALLING(capnum);
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}
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/**
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* @brief Disables capture on on falling edge of selected CAP signal. For the
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* selected capture register, disables the selected CAPn.capnum signal to load
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* the capture register with the terminal coount on a falling edge.
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* @param pTMR : Pointer to timer IP register address
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* @param capnum : Capture signal/register to use
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* @return Nothing
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*/
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STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
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{
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pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) & ~TIMER_CAP_FALLING(capnum);
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}
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/**
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* @brief Enables interrupt on capture of selected CAP signal. For the
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* selected capture register, an interrupt will be generated when the enabled
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* rising or falling edge on CAPn.capnum is detected.
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* @param pTMR : Pointer to timer IP register address
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* @param capnum : Capture signal/register to use
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* @return Nothing
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*/
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STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_T *pTMR, int8_t capnum)
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{
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pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) | TIMER_INT_ON_CAP(capnum);
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}
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/**
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* @brief Disables interrupt on capture of selected CAP signal
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* @param pTMR : Pointer to timer IP register address
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* @param capnum : Capture signal/register to use
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* @return Nothing
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*/
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STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_T *pTMR, int8_t capnum)
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{
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pTMR->CCR = (pTMR->CCR & TIMER_CCR_MASK) & ~TIMER_INT_ON_CAP(capnum);
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}
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/**
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* @brief Standard timer initial match pin state and change state
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*/
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typedef enum IP_TIMER_PIN_MATCH_STATE {
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TIMER_EXTMATCH_DO_NOTHING = 0, /*!< Timer match state does nothing on match pin */
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TIMER_EXTMATCH_CLEAR = 1, /*!< Timer match state sets match pin low */
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TIMER_EXTMATCH_SET = 2, /*!< Timer match state sets match pin high */
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TIMER_EXTMATCH_TOGGLE = 3 /*!< Timer match state toggles match pin */
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} TIMER_PIN_MATCH_STATE_T;
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/**
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* @brief Sets external match control (MATn.matchnum) pin control. For the pin
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* selected with matchnum, sets the function of the pin that occurs on
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* a terminal count match for the match count.
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* @param pTMR : Pointer to timer IP register address
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* @param initial_state : Initial state of the pin, high(1) or low(0)
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* @param matchState : Selects the match state for the pin
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* @param matchnum : MATn.matchnum signal to use
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* @return Nothing
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* @note For the pin selected with matchnum, sets the function of the pin that occurs on
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* a terminal count match for the match count.
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*/
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void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
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TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);
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/**
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* @brief Standard timer clock and edge for count source
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*/
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typedef enum IP_TIMER_CAP_SRC_STATE {
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TIMER_CAPSRC_RISING_PCLK = 0, /*!< Timer ticks on PCLK rising edge */
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TIMER_CAPSRC_RISING_CAPN = 1, /*!< Timer ticks on CAPn.x rising edge */
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TIMER_CAPSRC_FALLING_CAPN = 2, /*!< Timer ticks on CAPn.x falling edge */
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TIMER_CAPSRC_BOTH_CAPN = 3 /*!< Timer ticks on CAPn.x both edges */
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} TIMER_CAP_SRC_STATE_T;
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/**
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* @brief Sets timer count source and edge with the selected passed from CapSrc.
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* If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
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* @param pTMR : Pointer to timer IP register address
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* @param capSrc : timer clock source and edge
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* @param capnum : CAPn.capnum pin to use (0 - 2)
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* @return Nothing
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* @note If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
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*/
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STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_T *pTMR,
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TIMER_CAP_SRC_STATE_T capSrc,
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int8_t capnum)
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{
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pTMR->CTCR = (pTMR->CTCR & ~TIMER_CTCR_MASK) | ((uint32_t) capSrc | ((uint32_t) capnum) << 2);
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}
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __TIMER_5410X_H_ */
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