130 lines
3.2 KiB
C
130 lines
3.2 KiB
C
/*
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* Copyright (C) 2021, lizhengyang
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-09-02 lizhengyang first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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void rt_os_tick_callback(void)
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{
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rt_interrupt_enter();
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rt_tick_increase();
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rt_interrupt_leave();
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}
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void SysClkConfig(void)
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{
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stc_clk_sysclk_cfg_t stcSysClkCfg;
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stc_clk_xtal_cfg_t stcXtalCfg;
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stc_clk_mpll_cfg_t stcMpllCfg;
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stc_sram_config_t stcSramConfig;
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MEM_ZERO_STRUCT(stcSysClkCfg);
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MEM_ZERO_STRUCT(stcXtalCfg);
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MEM_ZERO_STRUCT(stcMpllCfg);
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/* Set bus clk div. */
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stcSysClkCfg.enHclkDiv = ClkSysclkDiv1;
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stcSysClkCfg.enExclkDiv = ClkSysclkDiv2;
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stcSysClkCfg.enPclk0Div = ClkSysclkDiv1;
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stcSysClkCfg.enPclk1Div = ClkSysclkDiv2;
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stcSysClkCfg.enPclk2Div = ClkSysclkDiv4;
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stcSysClkCfg.enPclk3Div = ClkSysclkDiv4;
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stcSysClkCfg.enPclk4Div = ClkSysclkDiv2;
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CLK_SysClkConfig(&stcSysClkCfg);
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/* Switch system clock source to MPLL. */
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/* Use Xtal as MPLL source. */
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stcXtalCfg.enMode = ClkXtalModeOsc;
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stcXtalCfg.enDrv = ClkXtalLowDrv;
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stcXtalCfg.enFastStartup = Enable;
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CLK_XtalConfig(&stcXtalCfg);
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CLK_XtalCmd(Enable);
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while (Set != CLK_GetFlagStatus(ClkFlagXTALRdy))
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{
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;
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}
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/* MPLL config. */
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stcMpllCfg.pllmDiv = 1ul;
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stcMpllCfg.plln = 50ul;
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stcMpllCfg.PllpDiv = 4ul;
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stcMpllCfg.PllqDiv = 4ul;
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stcMpllCfg.PllrDiv = 4ul;
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CLK_SetPllSource(ClkPllSrcXTAL);
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CLK_MpllConfig(&stcMpllCfg);
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/* flash read wait cycle setting */
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EFM_Unlock();
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EFM_SetLatency(5ul);
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EFM_Lock();
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/* sram init include read/write wait cycle setting */
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stcSramConfig.u8SramIdx = Sram12Idx | Sram3Idx | SramHsIdx | SramRetIdx;
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stcSramConfig.enSramRC = SramCycle2;
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stcSramConfig.enSramWC = SramCycle2;
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stcSramConfig.enSramEccMode = EccMode3;
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stcSramConfig.enSramEccOp = SramNmi;
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stcSramConfig.enSramPyOp = SramNmi;
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SRAM_Init(&stcSramConfig);
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/* Enable MPLL. */
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CLK_MpllCmd(Enable);
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/* Wait MPLL ready. */
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while (Set != CLK_GetFlagStatus(ClkFlagMPLLRdy))
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{
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;
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}
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/* Switch system clock source to MPLL. */
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CLK_SetSysClkSource(CLKSysSrcMPLL);
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}
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void SysTick_Handler(void)
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{
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rt_os_tick_callback();
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}
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/**
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* This function will initial your board.
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*/
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void rt_hw_board_init(void)
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{
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SysClkConfig();
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SysTick_Init(RT_TICK_PER_SECOND);
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/* Call components board initial (use INIT_BOARD_EXPORT()) */
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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}
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void rt_hw_us_delay(rt_uint32_t us)
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{
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uint32_t start, now, delta, reload, us_tick;
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start = SysTick->VAL;
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reload = SysTick->LOAD;
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us_tick = SystemCoreClock / 1000000UL;
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do
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{
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now = SysTick->VAL;
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delta = start > now ? start - now : reload + start - now;
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}
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while (delta < us_tick * us);
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}
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