376 lines
13 KiB
C
376 lines
13 KiB
C
/*
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* Copyright (C) Cvitek Co., Ltd. 2019-2029. All rights reserved.
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*/
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#ifndef __MMC_H__
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#define __MMC_H__
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <stdbool.h>
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#define TOP_BASE 0x03000000
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#define DW_SDIO0_BASE 0x04320000
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#define DW_SDIO1_BASE 0x04310000
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#define DW_SDIO2_BASE 0x04300000
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#define CONFIG_SDIO_NUM 3
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#define MMC_CMD0 0
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#define MMC_CMD1 1
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#define MMC_CMD2 2
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#define MMC_CMD3 3
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#define MMC_CMD5 5
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#define MMC_CMD6 6
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#define MMC_CMD7 7
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#define MMC_CMD8 8
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#define MMC_CMD9 9
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#define MMC_CMD11 11
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#define MMC_CMD12 12
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#define MMC_CMD13 13
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#define MMC_CMD16 16
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#define MMC_CMD17 17
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#define MMC_CMD18 18
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#define MMC_CMD19 19
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#define MMC_CMD21 21
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#define MMC_CMD23 23
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#define MMC_CMD24 24
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#define MMC_CMD25 25
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#define MMC_CMD32 32
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#define MMC_CMD33 33
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#define MMC_CMD35 35
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#define MMC_CMD36 36
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#define MMC_CMD38 38
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#define MMC_CMD52 52
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#define MMC_CMD53 53
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#define MMC_CMD55 55
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#define SD_ACMD6 6
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#define SD_ACMD13 13
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#define SD_ACMD41 41
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#define SD_ACMD42 42
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#define SD_ACMD51 51
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static inline int mmc_op_multi(uint32_t opcode)
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{
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return opcode == MMC_CMD25 || opcode == MMC_CMD18;
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}
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#define SDIO0_IRQ 36
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#define SDIO1_IRQ 38
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#define SDIO2_IRQ 34
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#define SDIO0_BASE DW_SDIO1_BASE
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#define SDIO1_BASE DW_SDIO0_BASE
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#define SDIO2_BASE DW_SDIO2_BASE
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#define SDIF_DMA_ADDRESS 0x00
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#define SDIF_BLOCK_SIZE 0x04
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#define SDIF_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF))
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#define SDIF_BLOCK_COUNT 0x06
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#define SDIF_ARGUMENT 0x08
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#define SDIF_TRANSFER_MODE 0x0C
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#define SDIF_TRNS_DMA BIT(0)
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#define SDIF_TRNS_BLK_CNT_EN BIT(1)
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#define SDIF_TRNS_ACMD12 BIT(2)
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#define SDIF_TRNS_READ BIT(4)
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#define SDIF_TRNS_MULTI BIT(5)
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#define SDIF_TRNS_RESP_INT BIT(8)
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#define SDIF_COMMAND 0x0E
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#define SDIF_CMD_RESP_MASK 0x03
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#define SDIF_CMD_CRC 0x08
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#define SDIF_CMD_INDEX 0x10
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#define SDIF_CMD_DATA 0x20
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#define SDIF_CMD_ABORTCMD 0xC0
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#define SDIF_CMD_RESP_NONE 0x00
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#define SDIF_CMD_RESP_LONG 0x01
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#define SDIF_CMD_RESP_SHORT 0x02
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#define SDIF_CMD_RESP_SHORT_BUSY 0x03
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#define SDIF_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
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#define SDIF_RESPONSE_01 0x10
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#define SDIF_RESPONSE_23 0x14
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#define SDIF_RESPONSE_45 0x18
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#define SDIF_RESPONSE_67 0x1C
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#define SDIF_RESPONSE 0x10
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#define SDIF_BUFFER 0x20
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#define SDIF_PRESENT_STATE 0x24
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#define SDIF_DATA_INHIBIT 0x00000002
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#define SDIF_DOING_WRITE 0x00000100
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#define SDIF_DOING_READ 0x00000200
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#define SDIF_SPACE_AVAILABLE 0x00000400
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#define SDIF_DATA_AVAILABLE 0x00000800
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#define SDIF_CARD_PRESENT 0x00010000
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#define SDIF_WRITE_PROTECT 0x00080000
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#define SDIF_DATA_LVL_MASK 0x00F00000
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#define SDIF_DATA_LVL_SHIFT 20
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#define SDIF_DATA_0_LVL_MASK 0x00100000
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#define SDIF_CMD_LVL 0x01000000
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#define SDIF_CMD_INHIBIT BIT(0)
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#define SDIF_CMD_INHIBIT_DAT BIT(1)
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#define SDIF_CARD_INSERTED BIT(16)
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#define SDIF_CARD_STABLE BIT(17)
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#define SDIF_WR_PROTECT_SW_LVL BIT(19)
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#define SDIF_DAT_XFER_WIDTH BIT(1)
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#define SDIF_CTRL_SDMA 0x00
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#define SDIF_CTRL_HISPD 0x04
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#define SDIF_BUS_VOL_VDD1_1_8V 0xC
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#define SDIF_BUS_VOL_VDD1_3_0V 0xE
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#define SDIF_CTRL_DMA_MASK 0x18
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#define SDIF_BUF_DATA_R 0x20
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#define SDIF_HOST_CONTROL 0x28
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#define SDIF_PWR_CONTROL 0x29
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#define SDIF_BLOCK_GAP_CONTROL 0x2A
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#define SDIF_WAKE_UP_CONTROL 0x2B
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#define SDIF_CLK_CTRL 0x2C
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#define SDIF_TOUT_CTRL 0x2E
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#define SDIF_SOFTWARE_RESET 0x2F
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#define SDIF_RESET_CMD 0x02
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#define SDIF_RESET_DATA 0x04
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#define SDIF_INT_STATUS 0x30
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#define SDIF_ERR_INT_STATUS 0x32
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#define SDIF_INT_ENABLE 0x34
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#define SDIF_INT_XFER_COMPLETE BIT(1)
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#define SDIF_INT_BUF_RD_READY BIT(5)
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#define SDIF_INT_STATUS_EN 0x34
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#define SDIF_ERR_INT_STATUS_EN 0x36
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#define SDIF_SIGNAL_ENABLE 0x38
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#define SDIF_ERROR_SIGNAL_ENABLE 0x3A
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#define SDIF_AUTO_CMD_STATUS 0x3C
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#define SDIF_HOST_CONTROL2 0x3E
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#define SDIF_CAPABILITIES 0x40
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#define SDIF_CAPABILITIES_1 0x44
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#define SDIF_MAX_CURRENT 0x48
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#define SDIF_ADMA_ERROR 0x54
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#define SDIF_ADMA_ADDRESS 0x58
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#define SDIF_ADMA_ADDRESS_HI 0x5C
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#define SDIF_SLOT_INT_STATUS 0xFC
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#define SDIF_HOST_VERSION 0xFE
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#define SDIF_INT_XFER_COMPLETE_EN BIT(1)
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#define SDIF_INT_DMA_END_EN BIT(3)
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#define SDIF_INT_ERROR_EN BIT(15)
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#define SDIF_HOST_ADMA2_LEN_MODE BIT(10)
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#define SDIF_CTRL_UHS_MASK 0x0007
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#define SDIF_CTRL_UHS_SDR12 0x0000
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#define SDIF_CTRL_UHS_SDR25 0x0001
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#define SDIF_CTRL_UHS_SDR50 0x0002
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#define SDIF_CTRL_UHS_SDR104 0x0003
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#define SDIF_CTRL_UHS_DDR50 0x0004
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#define SDIF_CTRL_HS400 0x0005 /* Non-standard */
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#define SDIF_CTRL_DRV_TYPE_MASK 0x0030
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#define SDIF_CTRL_DRV_TYPE_B 0x0000
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#define SDIF_CTRL_DRV_TYPE_A 0x0010
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#define SDIF_CTRL_DRV_TYPE_C 0x0020
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#define SDIF_CTRL_DRV_TYPE_D 0x0030
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#define SDIF_CTRL_EXEC_TUNING 0x0040
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#define SDIF_CTRL_TUNED_CLK 0x0080
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#define SDIF_CTRL_PRESET_VAL_ENABLE 0x8000
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#define SDIF_GET_CMD(c) ((c>>8) & 0x3f)
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#define SDIF_INT_RESPONSE 0x00000001
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#define SDIF_INT_DATA_END 0x00000002
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#define SDIF_INT_BLK_GAP 0x00000004
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#define SDIF_INT_DMA_END 0x00000008
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#define SDIF_INT_SPACE_AVAIL 0x00000010
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#define SDIF_INT_DATA_AVAIL 0x00000020
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#define SDIF_INT_CARD_INSERT 0x00000040
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#define SDIF_INT_CARD_REMOVE 0x00000080
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#define SDIF_INT_CARD_INT 0x00000100
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#define SDIF_INT_RETUNE 0x00001000
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#define SDIF_INT_ERROR 0x00008000
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#define SDIF_INT_TIMEOUT 0x00010000
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#define SDIF_INT_CRC 0x00020000
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#define SDIF_INT_END_BIT 0x00040000
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#define SDIF_INT_INDEX 0x00080000
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#define SDIF_INT_DATA_TIMEOUT 0x00100000
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#define SDIF_INT_DATA_CRC 0x00200000
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#define SDIF_INT_DATA_END_BIT 0x00400000
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#define SDIF_INT_BUS_POWER 0x00800000
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#define SDIF_INT_ACMD12ERR 0x01000000
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#define SDIF_INT_ADMA_ERROR 0x02000000
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#define SDIF_INT_CMD_MASK (SDIF_INT_RESPONSE | SDIF_INT_TIMEOUT | \
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SDIF_INT_CRC | SDIF_INT_END_BIT | SDIF_INT_INDEX)
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#define SDIF_INT_DATA_MASK (SDIF_INT_DATA_END | SDIF_INT_DMA_END | \
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SDIF_INT_DATA_AVAIL | SDIF_INT_SPACE_AVAIL | \
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SDIF_INT_DATA_TIMEOUT | SDIF_INT_DATA_CRC | \
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SDIF_INT_DATA_END_BIT | SDIF_INT_ADMA_ERROR | \
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SDIF_INT_BLK_GAP)
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#define SDIF_HOST_VER4_ENABLE BIT(12)
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#define SDIF_CAPABILITIES1 0x40
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#define SDIF_CAPABILITIES2 0x44
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#define SDIF_ADMA_SA_LOW 0x58
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#define SDIF_ADMA_SA_HIGH 0x5C
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#define SDIF_HOST_CNTRL_VERS 0xFE
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#define SDIF_UHS_2_TIMER_CNTRL 0xC2
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#define P_VENDOR_SPECIFIC_AREA 0xE8
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#define P_VENDOR2_SPECIFIC_AREA 0xEA
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#define VENDOR_SD_CTRL 0x2C
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#define DEFAULT_DIV_SD_INIT_CLOCK 0x2
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/*execute tuning register and bit flag*/
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#define SDIF_PHY_TX_RX_DLY 0x40
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#define SDIF_PHY_CONFIG 0x4c
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/*SDIO 0 register and bit flag*/
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#define REG_SDIO0_PAD_MASK (0xFFFFFFF3)
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#define REG_SDIO0_PAD_SHIFT (2)
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#define REG_SDIO0_CD_PAD_REG (PINMUX_BASE + 0x900)
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#define REG_SDIO0_CD_PAD_VALUE (1)
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#define REG_SDIO0_PWR_EN_PAD_REG (PINMUX_BASE + 0x904)
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#define REG_SDIO0_PWR_EN_PAD_VALUE (2)
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#define REG_SDIO0_CLK_PAD_REG (PINMUX_BASE + 0xA00)
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#define REG_SDIO0_CLK_PAD_VALUE (2)
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#define REG_SDIO0_CMD_PAD_REG (PINMUX_BASE + 0xA04)
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#define REG_SDIO0_CMD_PAD_VALUE (1)
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#define REG_SDIO0_DAT0_PAD_REG (PINMUX_BASE + 0xA08)
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#define REG_SDIO0_DAT0_PAD_VALUE (1)
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#define REG_SDIO0_DAT1_PAD_REG (PINMUX_BASE + 0xA0C)
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#define REG_SDIO0_DAT1_PAD_VALUE (1)
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#define REG_SDIO0_DAT2_PAD_REG (PINMUX_BASE + 0xA10)
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#define REG_SDIO0_DAT2_PAD_VALUE (1)
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#define REG_SDIO0_DAT3_PAD_REG (PINMUX_BASE + 0xA14)
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#define REG_SDIO0_DAT3_PAD_VALUE (1)
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#define REG_SDIO0_CD_PIO_REG (PINMUX_BASE + 0x34)
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#define REG_SDIO0_CD_PIO_VALUE (0x3)
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#define REG_SDIO0_PWR_EN_PIO_REG (PINMUX_BASE + 0x38)
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#define REG_SDIO0_PWR_EN_PIO_VALUE (0x0)
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#define REG_SDIO0_CLK_PIO_REG (PINMUX_BASE + 0x1C)
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#define REG_SDIO0_CLK_PIO_VALUE (0x0)
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#define REG_SDIO0_CMD_PIO_REG (PINMUX_BASE + 0x20)
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#define REG_SDIO0_CMD_PIO_VALUE (0x0)
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#define REG_SDIO0_DAT0_PIO_REG (PINMUX_BASE + 0x24)
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#define REG_SDIO0_DAT0_PIO_VALUE (0x0)
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#define REG_SDIO0_DAT1_PIO_REG (PINMUX_BASE + 0x28)
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#define REG_SDIO0_DAT1_PIO_VALUE (0x0)
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#define REG_SDIO0_DAT2_PIO_REG (PINMUX_BASE + 0x2C)
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#define REG_SDIO0_DAT2_PIO_VALUE (0x0)
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#define REG_SDIO0_DAT3_PIO_REG (PINMUX_BASE + 0x30)
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#define REG_SDIO0_DAT3_PIO_VALUE (0x0)
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/*SDIO 1 register and bit flag*/
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#define RTCIO_BASE (0x5027000)
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#define REG_SDIO1_PAD_MASK (0xFFFFFFF3)
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#define REG_SDIO1_PAD_SHIFT (2)
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#define REG_SDIO1_CLK_PAD_REG (RTCIO_BASE + 0x6C)
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#define REG_SDIO1_CLK_PAD_VALUE (2)
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#define REG_SDIO1_CMD_PAD_REG (RTCIO_BASE + 0x68)
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#define REG_SDIO1_CMD_PAD_VALUE (1)
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#define REG_SDIO1_DAT0_PAD_REG (RTCIO_BASE + 0x64)
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#define REG_SDIO1_DAT0_PAD_VALUE (1)
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#define REG_SDIO1_DAT1_PAD_REG (RTCIO_BASE + 0x60)
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#define REG_SDIO1_DAT1_PAD_VALUE (1)
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#define REG_SDIO1_DAT2_PAD_REG (RTCIO_BASE + 0x5C)
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#define REG_SDIO1_DAT2_PAD_VALUE (1)
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#define REG_SDIO1_DAT3_PAD_REG (RTCIO_BASE + 0x58)
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#define REG_SDIO1_DAT3_PAD_VALUE (1)
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#define REG_SDIO1_CLK_PIO_REG (PINMUX_BASE + 0xE4)
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#define REG_SDIO1_CLK_PIO_VALUE (0x0)
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#define REG_SDIO1_CMD_PIO_REG (PINMUX_BASE + 0xE0)
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#define REG_SDIO1_CMD_PIO_VALUE (0x0)
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#define REG_SDIO1_DAT0_PIO_REG (PINMUX_BASE + 0xDC)
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#define REG_SDIO1_DAT0_PIO_VALUE (0x0)
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#define REG_SDIO1_DAT1_PIO_REG (PINMUX_BASE + 0xD8)
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#define REG_SDIO1_DAT1_PIO_VALUE (0x0)
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#define REG_SDIO1_DAT2_PIO_REG (PINMUX_BASE + 0xD4)
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#define REG_SDIO1_DAT2_PIO_VALUE (0x0)
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#define REG_SDIO1_DAT3_PIO_REG (PINMUX_BASE + 0xD0)
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#define REG_SDIO1_DAT3_PIO_VALUE (0x0)
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#define RTC_CTRL_BASE 0x5025000
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#define RTCSYS_CLKMUX (RTC_CTRL_BASE + 0x1C)
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#define RTCSYS_CLKBYP (RTC_CTRL_BASE + 0x30)
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#define RTCSYS_MCU51_ICTRL1 (RTC_CTRL_BASE + 0x7C)
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#define RTCSYS_CTRL_BASE 0x03000000
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#define RTCSYS_CTRL (RTCSYS_CTRL_BASE + 0x248)
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/*SDIO 2 register and bit flag*/
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#define REG_SDIO2_PAD_MASK (0xFFFFFFF3)
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#define REG_SDIO2_PAD_SHIFT (2)
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#define REG_SDIO2_RSTN_PAD_REG (PINMUX_BASE + 0x914)
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#define REG_SDIO2_RSTN_PAD_VALUE (1)
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#define REG_SDIO2_CLK_PAD_REG (PINMUX_BASE + 0x91C)
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#define REG_SDIO2_CLK_PAD_VALUE (2)
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#define REG_SDIO2_CMD_PAD_REG (PINMUX_BASE + 0x928)
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#define REG_SDIO2_CMD_PAD_VALUE (1)
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#define REG_SDIO2_DAT0_PAD_REG (PINMUX_BASE + 0x920)
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#define REG_SDIO2_DAT0_PAD_VALUE (1)
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#define REG_SDIO2_DAT1_PAD_REG (PINMUX_BASE + 0x92C)
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#define REG_SDIO2_DAT1_PAD_VALUE (1)
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#define REG_SDIO2_DAT2_PAD_REG (PINMUX_BASE + 0x918)
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#define REG_SDIO2_DAT2_PAD_VALUE (1)
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#define REG_SDIO2_DAT3_PAD_REG (PINMUX_BASE + 0x924)
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#define REG_SDIO2_DAT3_PAD_VALUE (1)
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#define REG_SDIO2_RSTN_PIO_REG (PINMUX_BASE + 0x48)
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#define REG_SDIO2_RSTN_PIO_VALUE (0x0)
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#define REG_SDIO2_CLK_PIO_REG (PINMUX_BASE + 0x50)
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#define REG_SDIO2_CLK_PIO_VALUE (0x0)
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#define REG_SDIO2_CMD_PIO_REG (PINMUX_BASE + 0x5C)
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#define REG_SDIO2_CMD_PIO_VALUE (0x0)
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#define REG_SDIO2_DAT0_PIO_REG (PINMUX_BASE + 0x54)
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#define REG_SDIO2_DAT0_PIO_VALUE (0x0)
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#define REG_SDIO2_DAT1_PIO_REG (PINMUX_BASE + 0x60)
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#define REG_SDIO2_DAT1_PIO_VALUE (0x0)
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#define REG_SDIO2_DAT2_PIO_REG (PINMUX_BASE + 0x4C)
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#define REG_SDIO2_DAT2_PIO_VALUE (0x0)
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#define REG_SDIO2_DAT3_PIO_REG (PINMUX_BASE + 0x58)
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#define REG_SDIO2_DAT3_PIO_VALUE (0x0)
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#define MMC_SDIO0_PLL_REGISTER 0x3002070
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#define MMC_SDIO1_PLL_REGISTER 0x300207C
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#define MMC_SDIO2_PLL_REGISTER 0x3002064
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#define MMC_MAX_CLOCK_DIV_VALUE (0x40009)
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#define CLOCK_BYPASS_SELECT_REGISTER (0x3002030)
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#endif /* __HAL_DW_SDIO_H_ */
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