97 lines
3.0 KiB
C
97 lines
3.0 KiB
C
#ifndef __JZ47XX_H__
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#define __JZ47XX_H__
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#define __REG8(addr) *((volatile unsigned char *)(addr))
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#define __REG16(addr) *((volatile unsigned short *)(addr))
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#define __REG32(addr) *((volatile unsigned int *)(addr))
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#define HARB_BASE 0xB3000000
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#define EMC_BASE 0xB3010000
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#define DMAC_BASE 0xB3020000
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#define UHC_BASE 0xB3030000
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#define UDC_BASE 0xB3040000
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#define LCD_BASE 0xB3050000
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#define CIM_BASE 0xB3060000
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#define ETH_BASE 0xB3100000
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#define NBM_BASE 0xB3F00000
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#define CPM_BASE 0xB0000000
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#define INTC_BASE 0xB0001000
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#define OST_BASE 0xB0002000
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#define RTC_BASE 0xB0003000
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#define WDT_BASE 0xB0004000
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#define GPIO_BASE 0xB0010000
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#define AIC_BASE 0xB0020000
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#define MSC_BASE 0xB0021000
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#define UART0_BASE 0xB0030000
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#define UART1_BASE 0xB0031000
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#define UART2_BASE 0xB0032000
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#define UART3_BASE 0xB0033000
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#define FIR_BASE 0xB0040000
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#define SCC_BASE 0xB0041000
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#define SCC0_BASE 0xB0041000
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#define I2C_BASE 0xB0042000
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#define SSI_BASE 0xB0043000
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#define SCC1_BASE 0xB0044000
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#define PWM0_BASE 0xB0050000
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#define PWM1_BASE 0xB0051000
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#define DES_BASE 0xB0060000
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#define UPRT_BASE 0xB0061000
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#define KBC_BASE 0xB0062000
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/* uart offset */
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#define UART_RDR(base) __REG8((base) + 0x00) /* R 8b H'xx */
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#define UART_TDR(base) __REG8((base) + 0x00) /* W 8b H'xx */
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#define UART_DLLR(base) __REG8((base) + 0x00) /* RW 8b H'00 */
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#define UART_DLHR(base) __REG8((base) + 0x04) /* RW 8b H'00 */
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#define UART_IER(base) __REG8((base) + 0x04) /* RW 8b H'00 */
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#define UART_ISR(base) __REG8((base) + 0x08) /* R 8b H'01 */
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#define UART_FCR(base) __REG8((base) + 0x08) /* W 8b H'00 */
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#define UART_LCR(base) __REG8((base) + 0x0C) /* RW 8b H'00 */
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#define UART_MCR(base) __REG8((base) + 0x10) /* RW 8b H'00 */
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#define UART_LSR(base) __REG8((base) + 0x14) /* R 8b H'00 */
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#define UART_MSR(base) __REG8((base) + 0x18) /* R 8b H'00 */
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#define UART_SPR(base) __REG8((base) + 0x1C) /* RW 8b H'00 */
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#define UART_MCR(base) __REG8((base) + 0x10) /* RW 8b H'00 */
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#define UART_SIRCR(base) __REG8((base) + 0x20) /* RW 8b H'00 */
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/* interrupt controller */
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#define INTC_ISR __REG32(INTC_BASE + 0x00)
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#define INTC_IMR __REG32(INTC_BASE + 0x04)
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#define INTC_IMSR __REG32(INTC_BASE + 0x08)
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#define INTC_IMCR __REG32(INTC_BASE + 0x0c)
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#define INTC_IPR __REG32(INTC_BASE + 0x10)
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#define IRQ_I2C 1
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#define IRQ_PS2 2
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#define IRQ_UPRT 3
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#define IRQ_CORE 4
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#define IRQ_UART3 6
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#define IRQ_UART2 7
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#define IRQ_UART1 8
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#define IRQ_UART0 9
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#define IRQ_SCC1 10
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#define IRQ_SCC0 11
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#define IRQ_UDC 12
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#define IRQ_UHC 13
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#define IRQ_MSC 14
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#define IRQ_RTC 15
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#define IRQ_FIR 16
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#define IRQ_SSI 17
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#define IRQ_CIM 18
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#define IRQ_ETH 19
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#define IRQ_AIC 20
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#define IRQ_DMAC 21
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#define IRQ_OST2 22
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#define IRQ_OST1 23
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#define IRQ_OST0 24
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#define IRQ_GPIO3 25
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#define IRQ_GPIO2 26
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#define IRQ_GPIO1 27
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#define IRQ_GPIO0 28
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#define IRQ_LCD 30
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#define SYSTEM_STACK 0x8000ffe8 /* the kernel system stack address */
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#endif
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