219 lines
5.4 KiB
ArmAsm
219 lines
5.4 KiB
ArmAsm
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-05-17 swkyer first version
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* 2010-09-11 bernard port to Loongson SoC3210
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* 2011-08-08 lgnq port to Loongson LS1B
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* 2015-07-08 chinesebear port to Loongson LS1C
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* 2019-07-19 Zhou Yanjie clean up code
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*/
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__
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#endif
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#include <mips.h>
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#include "cache.h"
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.ent cache_init
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.global cache_init
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.set noreorder
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cache_init:
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move t1,ra
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####part 2####
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cache_detect_4way:
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mfc0 t4, CP0_CONFIG
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andi t5, t4, 0x0e00
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srl t5, t5, 9 #ic
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andi t6, t4, 0x01c0
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srl t6, t6, 6 #dc
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addiu t8, $0, 1
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addiu t9, $0, 2
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#set dcache way
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beq t6, $0, cache_d1way
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addiu t7, $0, 1 #1 way
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beq t6, t8, cache_d2way
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addiu t7, $0, 2 #2 way
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beq $0, $0, cache_d4way
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addiu t7, $0, 4 #4 way
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cache_d1way:
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beq $0, $0, 1f
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addiu t6, t6, 12 #1 way
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cache_d2way:
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beq $0, $0, 1f
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addiu t6, t6, 11 #2 way
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cache_d4way:
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addiu t6, t6, 10 #4 way (10), 2 way(11), 1 way(12)
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1: #set icache way
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beq t5, $0, cache_i1way
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addiu t3, $0, 1 #1 way
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beq t5, t8, cache_i2way
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addiu t3, $0, 2 #2 way
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beq $0, $0, cache_i4way
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addiu t3, $0, 4 #4 way
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cache_i1way:
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beq $0, $0, 1f
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addiu t5, t5, 12
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cache_i2way:
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beq $0, $0, 1f
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addiu t5, t5, 11
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cache_i4way:
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addiu t5, t5, 10 #4 way (10), 2 way(11), 1 way(12)
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1: addiu t4, $0, 1
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sllv t6, t4, t6
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sllv t5, t4, t5
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#if 0
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la t0, memvar
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sw t7, 0x0(t0) #ways
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sw t5, 0x4(t0) #icache size
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sw t6, 0x8(t0) #dcache size
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#endif
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####part 3####
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.set mips3
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lui a0, 0x8000
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addu a1, $0, t5
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addu a2, $0, t6
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cache_init_d2way:
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#a0=0x80000000, a1=icache_size, a2=dcache_size
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#a3, v0 and v1 used as local registers
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mtc0 $0, CP0_TAGHI
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addu v0, $0, a0
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addu v1, a0, a2
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1: slt a3, v0, v1
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beq a3, $0, 1f
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nop
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mtc0 $0, CP0_TAGLO
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beq t7, 1, 4f
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cache Index_Store_Tag_D, 0x0(v0) # 1 way
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beq t7, 2 ,4f
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cache Index_Store_Tag_D, 0x1(v0) # 2 way
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cache Index_Store_Tag_D, 0x2(v0) # 4 way
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cache Index_Store_Tag_D, 0x3(v0)
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4: beq $0, $0, 1b
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addiu v0, v0, 0x20
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1:
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cache_flush_i2way:
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addu v0, $0, a0
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addu v1, a0, a1
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1: slt a3, v0, v1
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beq a3, $0, 1f
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nop
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beq t3, 1, 4f
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cache Index_Invalidate_I, 0x0(v0) # 1 way
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beq t3, 2, 4f
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cache Index_Invalidate_I, 0x1(v0) # 2 way
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cache Index_Invalidate_I, 0x2(v0)
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cache Index_Invalidate_I, 0x3(v0) # 4 way
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4: beq $0, $0, 1b
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addiu v0, v0, 0x20
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1:
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cache_flush_d2way:
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addu v0, $0, a0
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addu v1, a0, a2
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1: slt a3, v0, v1
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beq a3, $0, 1f
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nop
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beq t7, 1, 4f
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cache Index_Writeback_Inv_D, 0x0(v0) #1 way
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beq t7, 2, 4f
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cache Index_Writeback_Inv_D, 0x1(v0) # 2 way
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cache Index_Writeback_Inv_D, 0x2(v0)
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cache Index_Writeback_Inv_D, 0x3(v0) # 4 way
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4: beq $0, $0, 1b
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addiu v0, v0, 0x20
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1:
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cache_init_finish:
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jr t1
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nop
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.set reorder
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.end cache_init
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###########################
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# Enable CPU cache #
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###########################
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LEAF(enable_cpu_cache)
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.set noreorder
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mfc0 t0, CP0_CONFIG
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nop
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and t0, ~0x03
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or t0, 0x03
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mtc0 t0, CP0_CONFIG
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nop
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.set reorder
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j ra
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END (enable_cpu_cache)
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###########################
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# disable CPU cache #
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###########################
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LEAF(disable_cpu_cache)
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.set noreorder
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mfc0 t0, CP0_CONFIG
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nop
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and t0, ~0x03
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or t0, 0x2
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mtc0 t0, CP0_CONFIG
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nop
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.set reorder
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j ra
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END (disable_cpu_cache)
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/**********************************/
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/* Invalidate Instruction Cache */
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/**********************************/
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LEAF(Clear_TagLo)
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.set noreorder
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mtc0 zero, CP0_TAGLO
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nop
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.set reorder
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j ra
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END(Clear_TagLo)
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.set mips3
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/**********************************/
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/* Invalidate Instruction Cache */
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/**********************************/
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LEAF(Invalidate_Icache_Ls1c)
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.set noreorder
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cache Index_Invalidate_I,0(a0)
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cache Index_Invalidate_I,1(a0)
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cache Index_Invalidate_I,2(a0)
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cache Index_Invalidate_I,3(a0)
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.set reorder
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j ra
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END(Invalidate_Icache_Ls1c)
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/**********************************/
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/* Invalidate Data Cache */
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/**********************************/
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LEAF(Invalidate_Dcache_ClearTag_Ls1c)
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.set noreorder
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cache Index_Store_Tag_D, 0(a0) # BDSLOT: clear tag
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cache Index_Store_Tag_D, 1(a0) # BDSLOT: clear tag
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.set reorder
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j ra
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END(Invalidate_Dcache_ClearTag_Ls1c)
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LEAF(Invalidate_Dcache_Fill_Ls1c)
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.set noreorder
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cache Index_Writeback_Inv_D, 0(a0) # BDSLOT: clear tag
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cache Index_Writeback_Inv_D, 1(a0) # BDSLOT: clear tag
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.set reorder
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j ra
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END(Invalidate_Dcache_Fill_Ls1c)
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LEAF(Writeback_Invalidate_Dcache)
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.set noreorder
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cache Hit_Writeback_Inv_D, (a0)
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.set reorder
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j ra
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END(Writeback_Invalidate_Dcache)
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.set mips0
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