99 lines
2.0 KiB
ArmAsm
99 lines
2.0 KiB
ArmAsm
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/01 Bernard The first version
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* 2018/12/27 Jesven Add SMP support
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* 2020/6/12 Xim Port to QEMU and remove SMP support
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*/
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#include <encoding.h>
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#include <cpuport.h>
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.data
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.global boot_hartid /* global varible rt_boot_hartid in .data section */
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boot_hartid:
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.word 0xdeadbeef
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.global _start
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.section ".start", "ax"
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_start:
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j 1f
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.word 0xdeadbeef
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.align 3
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.global g_wake_up
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g_wake_up:
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.dword 1
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.dword 0
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1:
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/* save hartid */
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la t0, boot_hartid /* global varible rt_boot_hartid */
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mv t1, a0 /* get hartid in S-mode frome a0 register */
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sw t1, (t0) /* store t1 register low 4 bits in memory address which is stored in t0 */
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/* clear Interrupt Registers */
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csrw sie, 0
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csrw sip, 0
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/* set Trap Vector Base Address Register */
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la t0, trap_entry
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csrw stvec, t0
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10,0
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li x11,0
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li x12,0
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li x13,0
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li x14,0
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li x15,0
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li x16,0
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li x17,0
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li x18,0
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li x19,0
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li x20,0
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li x21,0
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li x22,0
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li x23,0
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li x24,0
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li x25,0
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li x26,0
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li x27,0
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li x28,0
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li x29,0
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li x30,0
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li x31,0
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/* set to disable FPU */
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li t0, SSTATUS_FS + SSTATUS_VS
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csrc sstatus, t0
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li t0, SSTATUS_SUM
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csrs sstatus, t0
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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/* removed SMP support here */
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la sp, __stack_start__
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li t0, __STACKSIZE__
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add sp, sp, t0
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/**
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* sscratch is always zero on kernel mode
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*/
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csrw sscratch, zero
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call init_bss
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call sbi_init
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j primary_cpu_entry
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