114 lines
3.0 KiB
C
114 lines
3.0 KiB
C
/*
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* Copyright (c) 2021 hpmicro
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef ETH_PHY_PORT_H
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#define ETH_PHY_PORT_H
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#include "hpm_ioc_regs.h"
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#include <rtdevice.h>
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#ifndef PHY_AUTO_NEGO
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#define PHY_AUTO_NEGO (1U)
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#endif
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#ifndef PHY_MDIO_CSR_CLK_FREQ
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#define PHY_MDIO_CSR_CLK_FREQ (200000000U)
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#endif
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enum phy_link_status
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{
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PHY_LINK_DOWN = 0U,
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PHY_LINK_UP
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};
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typedef struct {
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rt_uint32_t phy_speed;
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rt_uint32_t phy_duplex;
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} phy_info_t;
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typedef struct {
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rt_uint32_t phy_link;
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rt_phy_t phy;
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phy_info_t phy_info;
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} phy_device_t;
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/** @note PHY: LAN8720A */
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#define PHY_NAME ("LAN8720A")
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#define PHY_ID1 (7U)
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/* The PHY basic control register */
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#define PHY_BASIC_CONTROL_REG (0x00U)
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#define PHY_RESET_MASK (1U << 15)
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#define PHY_AUTO_NEGOTIATION_MASK (1U << 12)
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/* The PHY basic status register */
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#define PHY_BASIC_STATUS_REG (0x01U)
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#define PHY_LINKED_STATUS_MASK (1U << 2)
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#define PHY_AUTONEGO_COMPLETE_MASK (1U << 5)
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/* The PHY ID one register */
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#define PHY_ID1_REG (0x02U)
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/* The PHY ID two register */
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#define PHY_ID2_REG (0x03U)
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/* The PHY auto-negotiate advertise register */
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#define PHY_AUTONEG_ADVERTISE_REG (0x04U)
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/* The PHY SPECIAL MODES REGISTER */
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#define PHY_SPECIAL_MODES_REG (0x12U)
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/* The PHY interrupt source flag register. */
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#define PHY_INTERRUPT_FLAG_REG (0x1dU)
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/* The PHY interrupt mask register. */
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#define PHY_INTERRUPT_MASK_REG (0x1eU)
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#define PHY_LINK_DOWN_MASK (1 << 4)
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#define PHY_AUTO_NEGO_COMPLETE_MASK (1 << 6)
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/* The PHY status register. */
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#define PHY_STATUS_REG (0x1fU)
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#define PHY_10M_MASK (1 << 2)
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#define PHY_100M_MASK (1 << 3)
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#define PHY_FULL_DUPLEX_MASK (1 << 4)
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#define PHY_STATUS_SPEED_10M(SR) ((SR) & PHY_10M_MASK)
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#define PHY_STATUS_SPEED_100M(SR) ((SR) & PHY_100M_MASK)
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#define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK)
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/* PHY0 register list */
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#define PHY0_REG_LIST PHY_BASIC_CONTROL_REG,\
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PHY_BASIC_STATUS_REG,\
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PHY_ID1_REG,\
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PHY_ID2_REG,\
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PHY_SPECIAL_MODES_REG,\
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PHY_INTERRUPT_FLAG_REG,\
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PHY_INTERRUPT_MASK_REG,\
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PHY_STATUS_REG
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/* PHY0 register index */
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#define PHY0_BASIC_STATUS_REG_IDX (1U)
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#define PHY0_ID1_REG_IDX (2U)
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#define PHY0_STATUS_REG_IDX (7U)
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/* PHY1 register list */
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#define PHY1_REG_LIST PHY_BASIC_CONTROL_REG,\
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PHY_BASIC_STATUS_REG,\
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PHY_ID1_REG,\
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PHY_ID2_REG,\
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PHY_SPECIAL_MODES_REG,\
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PHY_INTERRUPT_FLAG_REG,\
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PHY_INTERRUPT_MASK_REG,\
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PHY_STATUS_REG
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/* PHY1 register index */
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#define PHY_BASIC_STATUS_REG_IDX (1U)
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#define PHY_ID1_REG_IDX (2U)
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#define PHY_STATUS_REG_IDX (7U)
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#endif
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