427 lines
21 KiB
C
427 lines
21 KiB
C
/*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*/
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/******************************************************************************/
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/** \file hc32f460_spi.h
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**
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** A detailed description is available at
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** @link SpiGroup Serial Peripheral Interface description @endlink
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**
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** - 2018-10-29 CDT First version for Device Driver Library of Spi.
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**
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******************************************************************************/
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#ifndef __HC32F460_SPI_H__
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#define __HC32F460_SPI_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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#if (DDL_SPI_ENABLE == DDL_ON)
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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*******************************************************************************
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** \defgroup SpiGroup Serial Peripheral Interface(SPI)
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**
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******************************************************************************/
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//@{
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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*******************************************************************************
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** \brief SPI parity enumeration
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******************************************************************************/
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typedef enum en_spi_parity
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{
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SpiParityEven = 0u, ///< Select even parity send and receive
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SpiParityOdd = 1u, ///< Select odd parity send and receive
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} en_spi_parity_t;
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/**
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*******************************************************************************
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** \brief SPI master/slave mode enumeration
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******************************************************************************/
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typedef enum en_spi_master_slave_mode
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{
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SpiModeSlave = 0u, ///< Spi slave mode
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SpiModeMaster = 1u, ///< Spi master mode
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} en_spi_master_slave_mode_t;
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/**
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*******************************************************************************
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** \brief SPI transmission mode enumeration
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******************************************************************************/
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typedef enum en_spi_trans_mode
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{
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SpiTransFullDuplex = 0u, ///< Full duplex sync serial communication
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SpiTransOnlySend = 1u, ///< Only send serial communication
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} en_spi_trans_mode_t;
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/**
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*******************************************************************************
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** \brief SPI work mode enumeration
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******************************************************************************/
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typedef enum en_spi_work_mode
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{
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SpiWorkMode4Line = 0u, ///< 4 lines spi work mode
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SpiWorkMode3Line = 1u, ///< 3 lines spi work mode(clock sync running)
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} en_spi_work_mode_t;
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/**
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*******************************************************************************
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** \brief SPI SS interval time enumeration
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******************************************************************************/
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typedef enum en_spi_ss_interval_time
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{
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SpiSsIntervalSck1PlusPck2 = 0u, ///< Spi SS interval time 1 SCK plus 2 PCLK1
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SpiSsIntervalSck2PlusPck2 = 1u, ///< Spi SS interval time 2 SCK plus 2 PCLK1
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SpiSsIntervalSck3PlusPck2 = 2u, ///< Spi SS interval time 3 SCK plus 2 PCLK1
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SpiSsIntervalSck4PlusPck2 = 3u, ///< Spi SS interval time 4 SCK plus 2 PCLK1
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SpiSsIntervalSck5PlusPck2 = 4u, ///< Spi SS interval time 5 SCK plus 2 PCLK1
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SpiSsIntervalSck6PlusPck2 = 5u, ///< Spi SS interval time 6 SCK plus 2 PCLK1
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SpiSsIntervalSck7PlusPck2 = 6u, ///< Spi SS interval time 7 SCK plus 2 PCLK1
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SpiSsIntervalSck8PlusPck2 = 7u, ///< Spi SS interval time 8 SCK plus 2 PCLK1
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} en_spi_ss_interval_time_t;
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/**
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*******************************************************************************
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** \brief SPI SS setup delay SCK enumeration
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******************************************************************************/
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typedef enum en_spi_ss_setup_delay
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{
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SpiSsSetupDelaySck1 = 0u, ///< Spi SS setup delay 1 SCK
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SpiSsSetupDelaySck2 = 1u, ///< Spi SS setup delay 2 SCK
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SpiSsSetupDelaySck3 = 2u, ///< Spi SS setup delay 3 SCK
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SpiSsSetupDelaySck4 = 3u, ///< Spi SS setup delay 4 SCK
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SpiSsSetupDelaySck5 = 4u, ///< Spi SS setup delay 5 SCK
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SpiSsSetupDelaySck6 = 5u, ///< Spi SS setup delay 6 SCK
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SpiSsSetupDelaySck7 = 6u, ///< Spi SS setup delay 7 SCK
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SpiSsSetupDelaySck8 = 7u, ///< Spi SS setup delay 8 SCK
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} en_spi_ss_setup_delay_t;
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/**
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*******************************************************************************
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** \brief SPI SS hold delay SCK enumeration
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******************************************************************************/
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typedef enum en_spi_ss_hold_delay
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{
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SpiSsHoldDelaySck1 = 0u, ///< Spi SS hold delay 1 SCK
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SpiSsHoldDelaySck2 = 1u, ///< Spi SS hold delay 2 SCK
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SpiSsHoldDelaySck3 = 2u, ///< Spi SS hold delay 3 SCK
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SpiSsHoldDelaySck4 = 3u, ///< Spi SS hold delay 4 SCK
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SpiSsHoldDelaySck5 = 4u, ///< Spi SS hold delay 5 SCK
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SpiSsHoldDelaySck6 = 5u, ///< Spi SS hold delay 6 SCK
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SpiSsHoldDelaySck7 = 6u, ///< Spi SS hold delay 7 SCK
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SpiSsHoldDelaySck8 = 7u, ///< Spi SS hold delay 8 SCK
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} en_spi_ss_hold_delay_t;
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/**
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*******************************************************************************
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** \brief SPI slave select polarity enumeration
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******************************************************************************/
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typedef enum en_spi_ss_polarity
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{
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SpiSsLowValid = 0u, ///< SS0~3 signal low level valid
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SpiSsHighValid = 1u, ///< SS0~3 signal high level valid
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} en_spi_ss_polarity_t;
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/**
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*******************************************************************************
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** \brief SPI data register read object enumeration
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******************************************************************************/
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typedef enum en_spi_read_object
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{
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SpiReadReceiverBuffer = 0u, ///< Read receive buffer
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SpiReadSendBuffer = 1u, ///< Read send buffer(must be read when TDEF=1)
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} en_spi_read_object_t;
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/**
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*******************************************************************************
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** \brief SPI frame number enumeration
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******************************************************************************/
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typedef enum en_spi_frame_number
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{
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SpiFrameNumber1 = 0u, ///< 1 frame data
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SpiFrameNumber2 = 1u, ///< 2 frame data
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SpiFrameNumber3 = 2u, ///< 3 frame data
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SpiFrameNumber4 = 3u, ///< 4 frame data
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} en_spi_frame_number_t;
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/**
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*******************************************************************************
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** \brief SPI SS setup delay SCK option enumeration
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******************************************************************************/
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typedef enum en_spi_ss_setup_delay_option
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{
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SpiSsSetupDelayTypicalSck1 = 0u, ///< SS setup delay 1 SCK
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SpiSsSetupDelayCustomValue = 1u, ///< SS setup delay SCKDL register set value
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} en_spi_ss_setup_delay_option_t;
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/**
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*******************************************************************************
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** \brief SPI SS hold delay SCK option enumeration
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******************************************************************************/
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typedef enum en_spi_ss_hold_delay_option
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{
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SpiSsHoldDelayTypicalSck1 = 0u, ///< SS hold delay 1 SCK
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SpiSsHoldDelayCustomValue = 1u, ///< SS hold delay SSDL register set value
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} en_spi_ss_hold_delay_option_t;
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/**
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*******************************************************************************
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** \brief SPI SS interval time option enumeration
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******************************************************************************/
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typedef enum en_spi_ss_interval_time_option
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{
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SpiSsIntervalTypicalSck1PlusPck2 = 0u, ///< Spi SS interval time 1 SCK plus 2 PCLK1
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SpiSsIntervalCustomValue = 1u, ///< Spi SS interval time NXTDL register set value
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} en_spi_ss_interval_time_option_t;
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/**
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*******************************************************************************
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** \brief SPI first bit position enumeration
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******************************************************************************/
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typedef enum en_spi_first_bit_position
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{
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SpiFirstBitPositionMSB = 0u, ///< Spi first bit to MSB
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SpiFirstBitPositionLSB = 1u, ///< Spi first bit to LSB
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} en_spi_first_bit_position_t;
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/**
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*******************************************************************************
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** \brief SPI data length enumeration
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******************************************************************************/
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typedef enum en_spi_data_length
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{
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SpiDataLengthBit4 = 0u, ///< 4 bits
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SpiDataLengthBit5 = 1u, ///< 5 bits
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SpiDataLengthBit6 = 2u, ///< 6 bits
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SpiDataLengthBit7 = 3u, ///< 7 bits
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SpiDataLengthBit8 = 4u, ///< 8 bits
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SpiDataLengthBit9 = 5u, ///< 9 bits
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SpiDataLengthBit10 = 6u, ///< 10 bits
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SpiDataLengthBit11 = 7u, ///< 11 bits
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SpiDataLengthBit12 = 8u, ///< 12 bits
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SpiDataLengthBit13 = 9u, ///< 13 bits
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SpiDataLengthBit14 = 10u, ///< 14 bits
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SpiDataLengthBit15 = 11u, ///< 15 bits
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SpiDataLengthBit16 = 12u, ///< 16 bits
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SpiDataLengthBit20 = 13u, ///< 20 bits
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SpiDataLengthBit24 = 14u, ///< 24 bits
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SpiDataLengthBit32 = 15u, ///< 32 bits
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} en_spi_data_length_t;
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/**
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*******************************************************************************
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** \brief SPI SS valid channel select enumeration
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******************************************************************************/
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typedef enum en_spi_ss_valid_channel
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{
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SpiSsValidChannel0 = 0u, ///< Select SS0 valid
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SpiSsValidChannel1 = 1u, ///< Select SS1 valid
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SpiSsValidChannel2 = 2u, ///< Select SS2 valid
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SpiSsValidChannel3 = 3u, ///< Select SS3 valid
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} en_spi_ss_valid_channel_t;
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/**
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*******************************************************************************
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** \brief SPI clock division enumeration
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******************************************************************************/
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typedef enum en_spi_clk_div
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{
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SpiClkDiv2 = 0u, ///< Spi pclk1 division 2
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SpiClkDiv4 = 1u, ///< Spi pclk1 division 4
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SpiClkDiv8 = 2u, ///< Spi pclk1 division 8
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SpiClkDiv16 = 3u, ///< Spi pclk1 division 16
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SpiClkDiv32 = 4u, ///< Spi pclk1 division 32
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SpiClkDiv64 = 5u, ///< Spi pclk1 division 64
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SpiClkDiv128 = 6u, ///< Spi pclk1 division 128
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SpiClkDiv256 = 7u, ///< Spi pclk1 division 256
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} en_spi_clk_div_t;
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/**
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*******************************************************************************
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** \brief SPI SCK polarity enumeration
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******************************************************************************/
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typedef enum en_spi_sck_polarity
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{
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SpiSckIdleLevelLow = 0u, ///< SCK is low level when SCK idle
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SpiSckIdleLevelHigh = 1u, ///< SCK is high level when SCK idle
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} en_spi_sck_polarity_t;
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/**
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*******************************************************************************
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** \brief SPI SCK phase enumeration
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******************************************************************************/
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typedef enum en_spi_sck_phase
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{
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SpiSckOddSampleEvenChange = 0u, ///< SCK Odd edge data sample,even edge data change
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SpiSckOddChangeEvenSample = 1u, ///< SCK Odd edge data change,even edge data sample
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} en_spi_sck_phase_t;
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/**
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*******************************************************************************
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** \brief SPI interrupt request type enumeration
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******************************************************************************/
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typedef enum en_spi_irq_type
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{
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SpiIrqIdle = 0u, ///< Spi idle interrupt request
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SpiIrqReceive = 1u, ///< Spi receive interrupt request
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SpiIrqSend = 2u, ///< Spi send interrupt request
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SpiIrqError = 3u, ///< Spi error interrupt request
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} en_spi_irq_type_t;
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/**
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*******************************************************************************
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** \brief SPI flag type enumeration
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******************************************************************************/
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typedef enum en_spi_flag_type
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{
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SpiFlagReceiveBufferFull = 0u, ///< Receive buffer full flag
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SpiFlagSendBufferEmpty = 1u, ///< Send buffer empty flag
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SpiFlagUnderloadError = 2u, ///< Underload error flag
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SpiFlagParityError = 3u, ///< Parity error flag
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SpiFlagModeFaultError = 4u, ///< Mode fault error flag
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SpiFlagSpiIdle = 5u, ///< SPI idle flag
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SpiFlagOverloadError = 6u, ///< Overload error flag
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} en_spi_flag_type_t;
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/**
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*******************************************************************************
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** \brief SPI SS channel enumeration
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******************************************************************************/
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typedef enum en_spi_ss_channel
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{
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SpiSsChannel0 = 0u, ///< SS0 channel
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SpiSsChannel1 = 1u, ///< SS1 channel
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SpiSsChannel2 = 2u, ///< SS2 channel
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SpiSsChannel3 = 3u, ///< SS3 channel
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} en_spi_ss_channel_t;
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/**
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*******************************************************************************
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** \brief SPI bus delay structure definition
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**
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** \note Slave mode stc_spi_delay_config_t is invalid
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******************************************************************************/
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typedef struct stc_spi_delay_config
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{
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en_spi_ss_setup_delay_option_t enSsSetupDelayOption; ///< SS setup delay time option
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en_spi_ss_setup_delay_t enSsSetupDelayTime; ///< SS setup delay time(the value valid when enSsSetupDelayOption is custom)
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en_spi_ss_hold_delay_option_t enSsHoldDelayOption; ///< SS hold delay time option
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en_spi_ss_hold_delay_t enSsHoldDelayTime; ///< SS hold delay time(the value valid when enSsHoldDelayOption is custom)
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en_spi_ss_interval_time_option_t enSsIntervalTimeOption; ///< SS interval time option
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en_spi_ss_interval_time_t enSsIntervalTime; ///< SS interval time(the value valid when enSsIntervalTimeOption is custom)
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} stc_spi_delay_config_t;
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/**
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*******************************************************************************
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** \brief SPI SS config structure definition
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**
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** \note 3 lines mode stc_spi_ss_config_t is invalid
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******************************************************************************/
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typedef struct stc_spi_ss_config
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{
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en_spi_ss_valid_channel_t enSsValidBit; ///< SS valid channel select
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en_spi_ss_polarity_t enSs0Polarity; ///< SS0 signal polarity
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en_spi_ss_polarity_t enSs1Polarity; ///< SS1 signal polarity
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en_spi_ss_polarity_t enSs2Polarity; ///< SS2 signal polarity
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en_spi_ss_polarity_t enSs3Polarity; ///< SS3 signal polarity
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} stc_spi_ss_config_t;
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/**
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*******************************************************************************
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** \brief SPI init structure definition
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******************************************************************************/
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typedef struct stc_spi_init_t
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{
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stc_spi_delay_config_t stcDelayConfig; ///< SPI delay structure(Slave mode is invalid)
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stc_spi_ss_config_t stcSsConfig; ///< SS polarity and channel structure(3 lines mode invalid)
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en_spi_read_object_t enReadBufferObject; ///< Data register read object select(must be read when TDEF=1)
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en_spi_sck_polarity_t enSckPolarity; ///< Sck polarity
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en_spi_sck_phase_t enSckPhase; ///< Sck phase(This value must be SpiSckOddChangeEvenSample in 3-line mode)
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en_spi_clk_div_t enClkDiv; ///< SPI clock division
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en_spi_data_length_t enDataLength; ///< Data length
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en_spi_first_bit_position_t enFirstBitPosition; ///< Data first bit position
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en_spi_frame_number_t enFrameNumber; ///< Data frame number
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en_spi_work_mode_t enWorkMode; ///< Spi work mode
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en_spi_trans_mode_t enTransMode; ///< transmission mode
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en_spi_master_slave_mode_t enMasterSlaveMode; ///< Spi master/slave mode
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en_functional_state_t enCommAutoSuspendEn; ///< Enable/disable Communication auto suspend
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en_functional_state_t enModeFaultErrorDetectEn; ///< Enable/disable Mode fault error detect
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en_functional_state_t enParitySelfDetectEn; ///< Enable/disable Parity self detect
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en_functional_state_t enParityEn; ///< Enable/disable Parity(if enable parity and SPI_CR1.TXMDS=1, receive data don't parity)
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en_spi_parity_t enParity; ///< Parity mode select
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} stc_spi_init_t;
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/* Base functions */
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en_result_t SPI_DeInit(M4_SPI_TypeDef *SPIx);
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en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInitCfg);
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en_result_t SPI_GeneralLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta);
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en_result_t SPI_ReverseLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta);
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en_result_t SPI_Cmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta);
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/* Send and receive data functions */
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en_result_t SPI_SendData8(M4_SPI_TypeDef *SPIx, uint8_t u8Data);
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en_result_t SPI_SendData16(M4_SPI_TypeDef *SPIx, uint16_t u16Data);
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en_result_t SPI_SendData32(M4_SPI_TypeDef *SPIx, uint32_t u32Data);
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uint8_t SPI_ReceiveData8(const M4_SPI_TypeDef *SPIx);
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uint16_t SPI_ReceiveData16(const M4_SPI_TypeDef *SPIx);
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uint32_t SPI_ReceiveData32(const M4_SPI_TypeDef *SPIx);
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/* Communication configure functions */
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en_result_t SPI_SetSsPolarity(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel,
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en_spi_ss_polarity_t enPolarity);
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en_result_t SPI_SetSsValidChannel(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel);
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en_result_t SPI_SetReadDataRegObject(M4_SPI_TypeDef *SPIx, en_spi_read_object_t enObject);
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en_result_t SPI_SetFrameNumber(M4_SPI_TypeDef *SPIx, en_spi_frame_number_t enFrameNum);
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en_result_t SPI_SetDataLength(M4_SPI_TypeDef *SPIx, en_spi_data_length_t enDataLength);
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en_result_t SPI_SetFirstBitPosition(M4_SPI_TypeDef *SPIx, en_spi_first_bit_position_t enPosition);
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en_result_t SPI_SetClockDiv(M4_SPI_TypeDef *SPIx, en_spi_clk_div_t enClkDiv);
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/* Interrupt and flags functions */
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en_result_t SPI_IrqCmd(M4_SPI_TypeDef *SPIx, en_spi_irq_type_t enIrq,
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en_functional_state_t enNewSta);
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en_flag_status_t SPI_GetFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag);
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en_result_t SPI_ClearFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag);
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//@} // SpiGroup
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#ifdef __cplusplus
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}
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#endif
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#endif /* DDL_SPI_ENABLE */
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#endif /* __HC32F460_SPI_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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