66 lines
2.4 KiB
C
66 lines
2.4 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-04 zylx The first version for STM32F4xx
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*/
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#ifndef __SDRAM_PORT_H__
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#define __SDRAM_PORT_H__
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/* parameters for sdram peripheral */
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/* Bank1 or Bank2 */
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#define SDRAM_TARGET_BANK 1
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/* stm32h7 Bank1:0XC0000000 Bank2:0XD0000000 */
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#define SDRAM_BANK_ADDR ((uint32_t)0XC0000000)
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/* data width: 8, 16, 32 */
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#define SDRAM_DATA_WIDTH 16
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/* column bit numbers: 8, 9, 10, 11 */
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#define SDRAM_COLUMN_BITS 9
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/* row bit numbers: 11, 12, 13 */
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#define SDRAM_ROW_BITS 13
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/* cas latency clock number: 1, 2, 3 */
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#define SDRAM_CAS_LATENCY 2
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/* read pipe delay: 0, 1, 2 */
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#define SDRAM_RPIPE_DELAY 0
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/* clock divid: 2, 3 */
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#define SDCLOCK_PERIOD 2
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/* refresh rate counter */
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#define SDRAM_REFRESH_COUNT ((uint32_t)0x02A5)
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#define SDRAM_SIZE ((uint32_t)0x2000000)
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/* Timing configuration for W9825G6KH-6 */
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/* 100 MHz of HCKL3 clock frequency (200MHz/2) */
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/* TMRD: 2 Clock cycles */
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#define LOADTOACTIVEDELAY 2
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/* TXSR: 8x10ns */
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#define EXITSELFREFRESHDELAY 8
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/* TRAS: 5x10ns */
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#define SELFREFRESHTIME 6
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/* TRC: 7x10ns */
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#define ROWCYCLEDELAY 6
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/* TWR: 2 Clock cycles */
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#define WRITERECOVERYTIME 2
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/* TRP: 2x10ns */
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#define RPDELAY 2
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/* TRCD: 2x10ns */
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#define RCDDELAY 2
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/* memory mode register */
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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#endif
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