95 lines
3.3 KiB
C
95 lines
3.3 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-01-02 SummerGift first version
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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/* DMA1 channel1 */
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/* DMA1 channel2 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL)
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#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
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#define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn
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#endif
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/* DMA1 channel3 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL)
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#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI1_TX_DMA_INSTANCE DMA1_Channel3
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#define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
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#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL)
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#define USART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler
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#define USART3_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define USART3_RX_DMA_INSTANCE DMA1_Channel3
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#define USART3_RX_DMA_IRQ DMA1_Channel3_IRQn
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#endif
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/* DMA1 channel4 */
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#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL)
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#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_RX_DMA_INSTANCE DMA1_Channel4
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#define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn
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#endif
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/* DMA1 channel5 */
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#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL)
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#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
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#define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_TX_DMA_INSTANCE DMA1_Channel5
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#define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn
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#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL)
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#define USART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
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#define USART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define USART1_RX_DMA_INSTANCE DMA1_Channel5
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#define USART1_RX_DMA_IRQ DMA1_Channel5_IRQn
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#endif
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/* DMA1 channel6 */
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#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL)
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#define USART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler
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#define USART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define USART2_RX_DMA_INSTANCE DMA1_Channel6
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#define USART2_RX_DMA_IRQ DMA1_Channel6_IRQn
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#endif
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/* DMA1 channel7 */
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/* DMA2 channel1 */
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#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL)
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#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
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#define SPI3_RX_DMA_RCC RCC_AHBENR_DMA2EN
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#define SPI3_RX_DMA_INSTANCE DMA2_Channel1
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#define SPI3_RX_DMA_IRQ DMA2_Channel1_IRQn
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#endif
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/* DMA2 channel2 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL)
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#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
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#define SPI3_TX_DMA_RCC RCC_AHBENR_DMA2EN
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#define SPI3_TX_DMA_INSTANCE DMA2_Channel2
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#define SPI3_TX_DMA_IRQ DMA2_Channel2_IRQn
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/* DMA1 channel4 */
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#endif
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/* DMA2 channel3 */
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/* DMA2 channel4 */
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/* DMA2 channel5 */
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#endif /* __DMA_CONFIG_H__ */
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