451 lines
10 KiB
C
451 lines
10 KiB
C
/*
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* This file is part of FH8620 BSP for RT-Thread distribution.
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*
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* Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Visit http://www.fullhan.com to get contact with Fullhan.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#include "fh_def.h"
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#include "gpio.h"
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#include "Libraries/inc/fh_gpio.h"
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#include "interrupt.h"
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#include "board_info.h"
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#include <rtdevice.h>
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#include "fh_arch.h"
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//#define FH_GPIO_DEBUG
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#ifdef FH_GPIO_DEBUG
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#define PRINT_GPIO_DBG(fmt, args...) \
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do \
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{ \
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rt_kprintf("FH_GPIO_DEBUG: "); \
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rt_kprintf(fmt, ## args); \
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} \
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while(0)
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#else
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#define PRINT_GPIO_DBG(fmt, args...) do { } while (0)
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#endif
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int gpio_available[NUM_OF_GPIO];
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extern struct rt_irq_desc irq_desc[];
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static inline rt_uint32_t gpio_to_base(rt_uint32_t gpio)
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{
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if (gpio >= 32 && gpio < 64)
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{
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return GPIO1_REG_BASE;
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}
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else if(gpio < 32)
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{
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return GPIO0_REG_BASE;
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}
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else
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{
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rt_kprintf("ERROR: %s, incorrect GPIO num\n", __func__);
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return -RT_ERROR;
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}
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}
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static inline rt_uint32_t irq_to_base(rt_uint32_t irq)
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{
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return (irq-NR_INTERNAL_IRQS > 32) ? GPIO1_REG_BASE : GPIO0_REG_BASE;
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}
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static inline rt_uint32_t irq_to_bit(rt_uint32_t irq)
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{
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if(irq >= NR_INTERNAL_IRQS && irq < NR_INTERNAL_IRQS + 32)
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return 0;
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else
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return 32;
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}
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rt_uint32_t gpio_to_irq(rt_uint32_t gpio)
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{
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return (gpio + NR_INTERNAL_IRQS);
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}
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void gpio_enable_debounce(rt_uint32_t gpio)
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{
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rt_uint32_t tmp, base, offset;
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offset = gpio % 32;
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base = gpio_to_base(gpio);
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tmp = GET_REG(base + REG_GPIO_DEBOUNCE);
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tmp |= BIT(offset);
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SET_REG(base + REG_GPIO_DEBOUNCE, tmp);
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}
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void gpio_disable_debounce(rt_uint32_t gpio)
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{
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rt_uint32_t tmp, base, offset;
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offset = gpio % 32;
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base = gpio_to_base(gpio);
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tmp = GET_REG(base + REG_GPIO_DEBOUNCE);
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tmp &= ~BIT(offset);
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SET_REG(base + REG_GPIO_DEBOUNCE, tmp);
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}
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int gpio_get_value(rt_uint32_t gpio)
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{
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rt_uint32_t tmp, base, offset;
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offset = gpio % 32;
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base = gpio_to_base(gpio);
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tmp = GET_REG(base + REG_GPIO_SWPORTA_DDR);
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tmp &= BIT(offset);
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if (tmp) {
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tmp = GET_REG(base + REG_GPIO_SWPORTA_DR);
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} else {
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tmp = GET_REG(base + REG_GPIO_EXT_PORTA);
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}
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tmp &= BIT(offset);
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tmp = tmp >> offset;
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return tmp;
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}
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void gpio_set_value(rt_uint32_t gpio, int val)
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{
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rt_uint32_t tmp, base, offset;
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offset = gpio % 32;
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base = gpio_to_base(gpio);
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tmp = GET_REG(base + REG_GPIO_SWPORTA_DR);
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if(val)
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tmp |= BIT(offset);
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else
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tmp &= ~BIT(offset);
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SET_REG(base + REG_GPIO_SWPORTA_DR, tmp);
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}
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int gpio_get_direction(rt_uint32_t gpio)
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{
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rt_uint32_t tmp, base, offset;
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offset = gpio % 32;
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base = gpio_to_base(gpio);
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tmp = GET_REG(base + REG_GPIO_SWPORTA_DDR);
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tmp &= BIT(offset);
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tmp = tmp >> offset;
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return tmp;
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}
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void gpio_set_direction(rt_uint32_t gpio, rt_uint32_t direction)
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{
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rt_uint32_t tmp, base, offset;
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offset = gpio % 32;
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base = gpio_to_base(gpio);
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tmp = GET_REG(base + REG_GPIO_SWPORTA_DDR);
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if(direction == GPIO_DIR_OUTPUT)
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tmp |= BIT(offset);
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else
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tmp &= ~BIT(offset);
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SET_REG(base + REG_GPIO_SWPORTA_DDR, tmp);
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}
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int gpio_set_irq_type(rt_uint32_t gpio, rt_uint32_t type)
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{
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rt_uint32_t int_type, int_polarity;
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rt_uint32_t bit = gpio % 32;
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rt_uint32_t base;
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base = gpio_to_base(gpio);
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int_type = GET_REG(base + REG_GPIO_INTTYPE_LEVEL);
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int_polarity = GET_REG(base + REG_GPIO_INT_POLARITY);
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switch (type & IRQ_TYPE_TRIGGER_MASK) {
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case IRQ_TYPE_EDGE_BOTH:
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int_type |= BIT(bit);
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// toggle trigger
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if (gpio_get_value(gpio))
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int_polarity &= ~BIT(bit);
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else
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int_polarity |= BIT(bit);
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break;
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case IRQ_TYPE_EDGE_RISING:
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int_type |= BIT(bit);
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int_polarity |= BIT(bit);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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int_type |= BIT(bit);
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int_polarity &= ~BIT(bit);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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int_type &= ~BIT(bit);
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int_polarity |= BIT(bit);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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int_type &= ~BIT(bit);
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int_polarity &= ~BIT(bit);
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break;
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case IRQ_TYPE_NONE:
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return 0;
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default:
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return -RT_ERROR;
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}
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SET_REG(base + REG_GPIO_INTTYPE_LEVEL, int_type);
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SET_REG(base + REG_GPIO_INT_POLARITY, int_polarity);
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return 0;
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}
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int gpio_irq_mask(rt_uint32_t irq)
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{
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rt_uint32_t tmp, base, bit;
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base = irq_to_base(irq);
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bit = irq_to_bit(irq);
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tmp = GET_REG(base + REG_GPIO_INTMASK);
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tmp |= BIT(irq - NR_INTERNAL_IRQS - bit);
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SET_REG(base + REG_GPIO_INTMASK, tmp);
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return 0;
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}
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int gpio_irq_unmask(rt_uint32_t irq)
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{
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rt_uint32_t tmp, base, bit;
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base = irq_to_base(irq);
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bit = irq_to_bit(irq);
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tmp = GET_REG(base + REG_GPIO_INTMASK);
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tmp &= ~BIT((irq - NR_INTERNAL_IRQS - bit));
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SET_REG(base + REG_GPIO_INTMASK, tmp);
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return 0;
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}
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void gpio_irq_enable(rt_uint32_t irq)
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{
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rt_uint32_t tmp, base, bit;
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base = irq_to_base(irq);
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bit = irq_to_bit(irq);
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tmp = GET_REG(base + REG_GPIO_INTEN);
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tmp |= BIT(irq - NR_INTERNAL_IRQS - bit);
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SET_REG(base + REG_GPIO_INTEN, tmp);
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}
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void gpio_irq_disable(rt_uint32_t irq)
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{
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rt_uint32_t tmp, base, bit;
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base = irq_to_base(irq);
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bit = irq_to_bit(irq);
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tmp = GET_REG(base + REG_GPIO_INTEN);
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tmp &= ~BIT((irq - NR_INTERNAL_IRQS - bit));
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SET_REG(base + REG_GPIO_INTEN, tmp);
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}
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static void fh_gpio_interrupt(int irq, void *param)
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{
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rt_uint32_t irq_status;
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int gpio_num, gpio;
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rt_uint32_t base;
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struct fh_gpio_obj *gpio_obj = (struct fh_gpio_obj *)param;
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//rt_kprintf("fh_gpio_interrupt start\n");
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//fixme: spin lock???
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base = (irq==40) ? GPIO0_REG_BASE : GPIO1_REG_BASE;
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irq_status = GET_REG(base + REG_GPIO_INTSTATUS);
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if (irq_status == 0) {
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rt_kprintf("gpio irq status is zero.\n");
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return;
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}
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/* temporarily mask (level sensitive) parent IRQ */
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gpio_irq_mask(irq);
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gpio_num = __rt_ffs(irq_status) - 1;
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SET_REG(base + REG_GPIO_PORTA_EOI, BIT(gpio_num));
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gpio = gpio_num + ((irq==40) ? 0 : 32);
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//generic_handle_irq(gpio_to_irq(gpio));
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if(irq_desc[gpio_to_irq(gpio)].handler)
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irq_desc[gpio_to_irq(gpio)].handler(gpio_to_irq(gpio), irq_desc[gpio_to_irq(gpio)].param);
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gpio_irq_mask(irq);
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/* now it may re-trigger */
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}
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int gpio_direction_input(rt_uint32_t gpio)
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{
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rt_uint32_t reg, base;
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if(gpio > NUM_OF_GPIO)
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{
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rt_kprintf("ERROR: %s, incorrect GPIO num\n", __func__);
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return -RT_ERROR;
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}
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if(!gpio_available[gpio])
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{
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rt_kprintf("ERROR: %s, GPIO %d is not available\n", __func__, gpio);
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return -RT_EBUSY;
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}
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base = gpio_to_base(gpio);
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gpio = gpio % 32;
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//fixme: lock
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//spin_lock_irqsave(&chip->lock, flags);
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reg = GET_REG(base + REG_GPIO_SWPORTA_DDR);
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reg &= ~(1 << gpio);
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SET_REG(base + REG_GPIO_SWPORTA_DDR, reg);
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//spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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int gpio_direction_output(rt_uint32_t gpio, rt_uint32_t val)
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{
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rt_uint32_t reg, base;
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if(gpio > NUM_OF_GPIO)
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{
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rt_kprintf("ERROR: %s, incorrect GPIO num\n", __func__);
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return -RT_ERROR;
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}
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if(!gpio_available[gpio])
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{
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rt_kprintf("ERROR: %s, GPIO %d is not available\n", __func__, gpio);
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return -RT_EBUSY;
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}
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base = gpio_to_base(gpio);
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gpio = gpio % 32;
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//fixme: lock
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//spin_lock_irqsave(&chip->lock, flags);
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reg = GET_REG(base + REG_GPIO_SWPORTA_DDR);
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reg |= (1 << gpio);
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SET_REG(base + REG_GPIO_SWPORTA_DDR, reg);
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reg = GET_REG(base + REG_GPIO_SWPORTA_DR);
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if(val)
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reg |= (1 << gpio);
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else
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reg &= ~(1 << gpio);
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SET_REG(base + REG_GPIO_SWPORTA_DR, reg);
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//spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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int gpio_request(rt_uint32_t gpio)
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{
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if(gpio > NUM_OF_GPIO)
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{
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rt_kprintf("ERROR: %s, incorrect GPIO num\n", __func__);
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return -RT_ERROR;
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}
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gpio_available[gpio] = 1;
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return 0;
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}
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int gpio_release(rt_uint32_t gpio)
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{
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if(gpio > NUM_OF_GPIO)
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{
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rt_kprintf("ERROR: %s, incorrect GPIO num\n", __func__);
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return -RT_ERROR;
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}
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gpio_available[gpio] = 0;
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return 0;
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}
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int fh_gpio_probe(void *priv_data)
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{
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struct fh_gpio_obj *gpio_obj = (struct fh_gpio_obj *)priv_data;
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int i;
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if(gpio_obj->id == 0){
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rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_0");
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}
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else if(gpio_obj->id == 1){
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rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_1");
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}
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rt_hw_interrupt_umask(gpio_obj->irq);
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for(i=0; i<32; i++)
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{
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irq_desc[NR_INTERNAL_IRQS + 32 * gpio_obj->id + i].param = gpio_obj;
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}
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return 0;
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}
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int fh_gpio_exit(void *priv_data)
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{
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return 0;
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}
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struct fh_board_ops gpio_driver_ops =
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{
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.probe = fh_gpio_probe,
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.exit = fh_gpio_exit,
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};
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void rt_hw_gpio_init(void)
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{
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PRINT_GPIO_DBG("%s start\n", __func__);
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rt_memset(gpio_available, 0, sizeof(int) * NUM_OF_GPIO);
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fh_board_driver_register("gpio", &gpio_driver_ops);
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PRINT_GPIO_DBG("%s end\n", __func__);
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}
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