400 lines
10 KiB
C
400 lines
10 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-07-15 Emuzit first version
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*/
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#include <rthw.h>
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#include <rtdebug.h>
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#include <drivers/pin.h>
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#include "ch56x_gpio.h"
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#include "isr_sp.h"
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struct port_info
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{
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uint32_t pin_mark;
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struct gpio_px_regs *regbase;
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};
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static const struct port_info pin_ports[GPIO_PORTS] =
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{
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{GPIO_PA_PIN_MARK, (struct gpio_px_regs *)GPIO_REG_BASE_PA},
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{GPIO_PB_PIN_MARK, (struct gpio_px_regs *)GPIO_REG_BASE_PB},
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};
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static struct rt_pin_irq_hdr pin_irq_hdr_table[8] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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#if defined(SOC_SERIES_CH569)
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static int _gpio_pin_to_ibit(rt_base_t pin)
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{
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/* gpio ext interrupt 7-0 : {PB15,PB12,PB11,PB4,PB3,PA4,PA3,PA2}
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* not time critical, use linear search
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*/
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switch (pin)
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{
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case GET_PIN(A, 2): return 0;
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case GET_PIN(A, 3): return 1;
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case GET_PIN(A, 4): return 2;
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case GET_PIN(B, 3): return 3;
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case GET_PIN(B, 4): return 4;
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case GET_PIN(B, 11): return 5;
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case GET_PIN(B, 12): return 6;
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case GET_PIN(B, 15): return 7;
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}
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return -1;
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}
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#else
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static int _gpio_pin_to_ibit(rt_base_t pin)
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{
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/* gpio ext interrupt 7-0 : {PB10,PB4,PA12,PA11,PA10,PA6,PA4,PA3}
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* not time critical, use linear search
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*/
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switch (pin)
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{
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case GET_PIN(A, 3): return 0;
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case GET_PIN(A, 4): return 1;
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case GET_PIN(A, 6): return 2;
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case GET_PIN(A, 10): return 3;
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case GET_PIN(A, 11): return 4;
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case GET_PIN(A, 12): return 5;
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case GET_PIN(B, 4): return 6;
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case GET_PIN(B, 10): return 7;
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}
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return -1;
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}
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#endif
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static struct gpio_px_regs *_gpio_px_regbase(rt_base_t pin)
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{
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/* fixed linear mapping : 32 pins per port, for ports A,B,C,D...
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*/
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uint32_t port = (uint32_t)pin >> 5;
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uint32_t bitpos = 1 << (pin & 0x1f);
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if (port < GPIO_PORTS && (pin_ports[port].pin_mark & bitpos))
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return pin_ports[port].regbase;
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else
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return RT_NULL;
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}
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static void gpio_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
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{
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volatile struct gpio_px_regs *px;
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uint32_t port = (uint32_t)pin >> 5;
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uint32_t bitpos = 1 << (pin & 0x1f);
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if (port < GPIO_PORTS && (pin_ports[port].pin_mark & bitpos))
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px = pin_ports[port].regbase;
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else
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return;
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switch (mode)
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{
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case PIN_MODE_OUTPUT:
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BITS_CLR(px->PD, bitpos);
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BITS_SET(px->DIR, bitpos);
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break;
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case PIN_MODE_INPUT:
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BITS_CLR(px->PU, bitpos);
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BITS_CLR(px->PD, bitpos);
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BITS_CLR(px->DIR, bitpos);
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break;
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case PIN_MODE_INPUT_PULLUP:
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BITS_SET(px->PU, bitpos);
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BITS_CLR(px->PD, bitpos);
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BITS_CLR(px->DIR, bitpos);
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break;
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case PIN_MODE_INPUT_PULLDOWN:
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BITS_CLR(px->PU, bitpos);
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BITS_SET(px->PD, bitpos);
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BITS_CLR(px->DIR, bitpos);
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break;
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case PIN_MODE_OUTPUT_OD:
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BITS_SET(px->PD, bitpos);
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BITS_SET(px->OUT, bitpos);
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}
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}
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static void gpio_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
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{
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volatile struct gpio_px_regs *px;
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uint32_t port = (uint32_t)pin >> 5;
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uint32_t bitpos = 1 << (pin & 0x1f);
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if (port < GPIO_PORTS && (pin_ports[port].pin_mark & bitpos))
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px = pin_ports[port].regbase;
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else
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return;
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if (value == 0)
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BITS_CLR(px->OUT, bitpos);
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else
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BITS_SET(px->OUT, bitpos);
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}
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static rt_int8_t gpio_pin_read(struct rt_device *device, rt_base_t pin)
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{
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volatile struct gpio_px_regs *px;
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uint32_t port = (uint32_t)pin >> 5;
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uint32_t bitpos = 1 << (pin & 0x1f);
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if (port < GPIO_PORTS && (pin_ports[port].pin_mark & bitpos))
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px = pin_ports[port].regbase;
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else
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return PIN_LOW;
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return (px->PIN & bitpos) ? PIN_HIGH : PIN_LOW;
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}
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static rt_base_t gpio_pin_get(const char *name)
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{
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int port, pin, sz, n;
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/* pin name is in the form "PX.nn" (X: A,B,C,D...; nn: 0~31)
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* fixed linear mapping : 32 pins per port, for ports A,B,C,D...
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*/
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sz = rt_strlen(name);
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if ((sz == 4 || sz == 5) && name[0] == 'P' && name[2] == '.')
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{
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port = name[1] - 'A';
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pin = name[3] - '0';
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if (0 <= port && port < GPIO_PORTS && 0 <= pin && pin <= 9)
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{
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if (sz == 5)
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{
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n = name[4] - '0';
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pin = (0 <= n && n <= 9) ? (pin * 10 + n) : 32;
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}
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if (pin < 32 && (pin_ports[port].pin_mark & (1 << pin)))
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{
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return port * 32 + pin;
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}
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}
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}
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return -1;
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}
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static rt_err_t gpio_pin_attach_irq(struct rt_device *device, rt_base_t pin,
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rt_uint8_t mode, void (*hdr)(void *args), void *args)
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{
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rt_base_t level;
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int ibit;
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switch (mode)
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{
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case PIN_IRQ_MODE_RISING:
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case PIN_IRQ_MODE_FALLING:
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case PIN_IRQ_MODE_HIGH_LEVEL:
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case PIN_IRQ_MODE_LOW_LEVEL:
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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/* hardware not supported */
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default:
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return -RT_EINVAL;
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}
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ibit = _gpio_pin_to_ibit(pin);
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if (ibit < 0)
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return -RT_EINVAL;
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_table[ibit].pin == pin &&
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pin_irq_hdr_table[ibit].mode == mode &&
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pin_irq_hdr_table[ibit].hdr == hdr &&
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pin_irq_hdr_table[ibit].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_table[ibit].pin >= 0)
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{
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rt_hw_interrupt_enable(level);
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return -RT_EFULL;
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}
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pin_irq_hdr_table[ibit].pin = pin;
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pin_irq_hdr_table[ibit].mode = mode;
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pin_irq_hdr_table[ibit].hdr = hdr;
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pin_irq_hdr_table[ibit].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t gpio_pin_detach_irq(struct rt_device *device, rt_base_t pin)
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{
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rt_base_t level;
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int ibit;
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ibit = _gpio_pin_to_ibit(pin);
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if (ibit < 0)
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return -RT_EINVAL;
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_table[ibit].pin < 0)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_table[ibit].pin = -1;
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pin_irq_hdr_table[ibit].mode = 0;
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pin_irq_hdr_table[ibit].hdr = RT_NULL;
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pin_irq_hdr_table[ibit].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t gpio_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint8_t enabled)
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{
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volatile struct gpio_registers *gpio;
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rt_base_t level, int_enable;
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int ibit, bitpos;
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ibit = _gpio_pin_to_ibit(pin);
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if (ibit < 0)
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return -RT_EINVAL;
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bitpos = (1 << ibit);
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gpio = (struct gpio_registers *)GPIO_REG_BASE;
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if (enabled == PIN_IRQ_ENABLE)
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{
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_table[ibit].pin != pin)
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{
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rt_hw_interrupt_enable(level);
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return -RT_EINVAL;
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}
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switch (pin_irq_hdr_table[ibit].mode)
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{
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case PIN_IRQ_MODE_RISING:
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BITS_SET(gpio->INT_MODE.reg, bitpos);
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BITS_SET(gpio->INT_POLAR.reg, bitpos);
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break;
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case PIN_IRQ_MODE_FALLING:
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BITS_SET(gpio->INT_MODE.reg, bitpos);
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BITS_CLR(gpio->INT_POLAR.reg, bitpos);
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break;
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case PIN_IRQ_MODE_HIGH_LEVEL:
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BITS_CLR(gpio->INT_MODE.reg, bitpos);
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BITS_SET(gpio->INT_POLAR.reg, bitpos);
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break;
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case PIN_IRQ_MODE_LOW_LEVEL:
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BITS_CLR(gpio->INT_MODE.reg, bitpos);
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BITS_CLR(gpio->INT_POLAR.reg, bitpos);
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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default:
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rt_hw_interrupt_enable(level);
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return -RT_EINVAL;
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}
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/* clear possible pending intr, then enable pin intr */
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int_enable = gpio->INT_ENABLE.reg;
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gpio->INT_FLAG.reg = bitpos;
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gpio->INT_ENABLE.reg = int_enable | bitpos;
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/* enable GPIO_IRQn if this is the first enabled EXTIx */
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if (int_enable == 0)
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{
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rt_hw_interrupt_umask(GPIO_IRQn);
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}
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rt_hw_interrupt_enable(level);
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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level = rt_hw_interrupt_disable();
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int_enable = gpio->INT_ENABLE.reg;
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BITS_CLR(int_enable, bitpos);
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gpio->INT_ENABLE.reg = int_enable;
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/* disable GPIO_IRQn if no EXTIx enabled */
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if (int_enable == 0)
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{
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rt_hw_interrupt_mask(GPIO_IRQn);
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}
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rt_hw_interrupt_enable(level);
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}
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else
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{
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return -RT_EINVAL;
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}
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return RT_EOK;
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}
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static const struct rt_pin_ops pin_ops =
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{
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.pin_mode = gpio_pin_mode,
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.pin_write = gpio_pin_write,
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.pin_read = gpio_pin_read,
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.pin_attach_irq = gpio_pin_attach_irq,
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.pin_detach_irq = gpio_pin_detach_irq,
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.pin_irq_enable = gpio_pin_irq_enable,
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.pin_get = gpio_pin_get,
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};
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static int rt_hw_pin_init(void)
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{
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return rt_device_pin_register("pin", &pin_ops, RT_NULL);
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}
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INIT_BOARD_EXPORT(rt_hw_pin_init);
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void gpio_irq_handler(void) __attribute__((interrupt()));
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void gpio_irq_handler(void)
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{
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volatile struct gpio_registers *gpio;
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uint8_t iflags;
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int ibit, bitpos;
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isr_sp_enter();
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rt_interrupt_enter();
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gpio = (struct gpio_registers *)GPIO_REG_BASE;
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iflags = gpio->INT_FLAG.reg;
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/* prioritized as pb15 -> pa2 (CH569), or pb10 -> pa3 */
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for (ibit = 7; ibit >= 0; ibit--)
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{
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bitpos = (1 << ibit);
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if (iflags & bitpos)
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{
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if (pin_irq_hdr_table[ibit].hdr)
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{
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pin_irq_hdr_table[ibit].hdr(pin_irq_hdr_table[ibit].args);
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}
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/* clear interrupt */
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gpio->INT_FLAG.reg = bitpos;
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}
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}
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rt_interrupt_leave();
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isr_sp_leave();
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}
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