75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
/*
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* Misc define for GS232
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*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-12-04 Jiaxun Yang Initial version
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*/
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#ifndef __GS232_H__
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#define __GS232_H__
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#include <mips.h>
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#define INTC_BASE 0xBFD01040
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#ifdef SOC_LS1B
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#define GS232_INTC_CELLS 4
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#endif
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#ifdef SOC_LS1C300
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#define GS232_INTC_CELLS 5
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#endif
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#define GS232_NR_IRQS (32 * GS232_INTC_CELLS)
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#define GMAC0_BASE 0xBFE10000
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#define GMAC0_DMA_BASE 0xBFE11000
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#define GMAC1_BASE 0xBFE20000
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#define GMAC1_DMA_BASE 0xBFE21000
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#define I2C0_BASE 0xBFE58000
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#define PWM0_BASE 0xBFE5C000
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#define PWM1_BASE 0xBFE5C010
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#define PWM2_BASE 0xBFE5C020
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#define PWM3_BASE 0xBFE5C030
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#define WDT_BASE 0xBFE5C060
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#define RTC_BASE 0xBFE64000
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#define I2C1_BASE 0xBFE68000
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#define I2C2_BASE 0xBFE70000
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#define AC97_BASE 0xBFE74000
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#define NAND_BASE 0xBFE78000
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#define SPI_BASE 0xBFE80000
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#define CAN1_BASE 0xBF004300
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#define CAN0_BASE 0xBF004400
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#ifndef __ASSEMBLY__
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#include <rthw.h>
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/* Watch Dog registers */
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#define WDT_EN HWREG32(WDT_BASE + 0x00)
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#define WDT_SET HWREG32(WDT_BASE + 0x08)
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#define WDT_TIMER HWREG32(WDT_BASE + 0x04)
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#define PLL_FREQ HWREG32(0xbfe78030)
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#define PLL_DIV_PARAM HWREG32(0xbfe78034)
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struct gs232_intc_regs
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{
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volatile unsigned int int_isr;
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volatile unsigned int int_en;
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volatile unsigned int int_set;
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volatile unsigned int int_clr; /* offset 0x10*/
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volatile unsigned int int_pol;
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volatile unsigned int int_edge; /* offset 0 */
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};
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extern void rt_hw_timer_init(void);
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#endif
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#endif
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