431 lines
17 KiB
C
431 lines
17 KiB
C
/**
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*******************************************************************************
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* @file hc32f4a0_qspi.h
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* @brief This file contains all the functions prototypes of the QSPI driver
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* library.
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@verbatim
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Change Logs:
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Date Author Notes
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2020-06-12 Wuze First version
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2020-07-15 Wuze Corrected the definition of 'QSPI_4BIC_ENABLE'.
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __HC32F4A0_QSPI_H__
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#define __HC32F4A0_QSPI_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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/**
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* @addtogroup HC32F4A0_DDL_Driver
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* @{
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*/
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/**
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* @addtogroup DDL_QSPI
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* @{
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*/
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#if (DDL_QSPI_ENABLE == DDL_ON)
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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* @defgroup QSPI_Global_Types QSPI Global Types
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* @{
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*/
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/**
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* @brief QSPI initialization structure.
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*/
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typedef struct
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{
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uint32_t u32ClkDiv; /*!< Specifies the clock divider for QSCK. QSCK = HCLK / u32ClkDiv.
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This parameter can be a value between 2U and 64U, inclusive. */
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uint32_t u32CSSetupTiming; /*!< Specifies the setup timing of CS.
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This parameter can be a value of @ref QSPI_CS_Setup_Timing */
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uint32_t u32CSReleaseTiming; /*!< Specifies the hold timing of CS.
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This parameter can be a value of @ref QSPI_CS_Release_Timing */
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uint32_t u32CSIdleTime; /*!< Specifies the minimum idle time for CS. CS needs idle(stay high) for several cycles between commands.
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This parameter can be a value of between 1U and 16U, inclusive. */
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uint32_t u32CSExtendTime; /*!< Extend the time of chip-select signal after SPI bus access.
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This parameter can be a value of @ref QSPI_CS_Extend_Time */
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uint32_t u32SPIMode; /*!< Specifies the SPI mode. The difference between SPI modes 0 and 3 is the standby level of the QSCK signal.
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The standby level of the QSCK signal in SPI mode 0 is low, and high in SPI mode 3.
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This parameter can be a value of @ref QSPI_SPI_Mode */
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uint32_t u32PrefetchCmd; /*!< Enable or disable prefeth function.
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This parameter can be a value of @ref QSPI_Prefetch_Cmd */
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uint32_t u32PrefetchStopPos; /*!< Specifies the position of prefetch stop.
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This parameter can be a value of @ref QSPI_Prefetch_Stop_Position */
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uint32_t u32WPLevel; /*!< Specifies the level of pin WP(IO2).
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This parameter can be a value of @ref QSPI_WP_Level */
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uint32_t u32CommMode; /*!< Specifies the communication mode.
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This parameter can be a value of @ref QSPI_Communication_Mode */
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uint32_t u32AddrWidth; /*!< Specifies the address width.
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This parameter can be a value of @ref QSPI_Addr_Width */
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uint32_t u32InstrMode; /*!< Specifies the instruction mode.
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This parameter can be a value of @ref QSPI_Instruction_Mode */
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uint32_t u32AddrMode; /*!< Specifies the address mode.
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This parameter can be a value of @ref QSPI_Addr_Mode */
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uint32_t u32DataMode; /*!< Specifies the data mode (used for dummy cycles and data phases)
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This parameter can be a value of @ref QSPI_Data_Mode */
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uint32_t u32ReadMode; /*!< Specifies the read mode.
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This parameter can be a value of @ref QSPI_Read_Mode */
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uint8_t u8RomAccessInstr; /*!< Rom access instruction. This parameter only supports read instruction of QSPI flash now.
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Tis instruction must correspond to the read mode that specified by parameter 'u32ReadMode'. */
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uint32_t u32DummyCycles; /*!< Specifies the number of dummy cycles for fast read.
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This parameter can be a value between 3U and 18U. */
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} stc_qspi_init_t;
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/**
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* @}
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*/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup QSPI_Global_Macros QSPI Global Macros
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* @{
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*/
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/**
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* @defgroup QSPI_Read_Mode QSPI Read Mode
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* @{
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*/
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#define QSPI_READ_STANDARD_READ (0x0U) /*!< Standard read mode (no dummy cycles). */
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#define QSPI_READ_FAST_READ (QSPI_CR_MDSEL_0) /*!< Fast read mode (dummy cycles between address and data). */
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#define QSPI_READ_FAST_READ_DUAL_OUTPUT (QSPI_CR_MDSEL_1) /*!< Fast read dual output mode (data on 2 lines). */
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#define QSPI_READ_FAST_READ_DUAL_IO (QSPI_CR_MDSEL_1 | \
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QSPI_CR_MDSEL_0) /*!< Fast read dual I/O mode (address and data on 2 lines). */
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#define QSPI_READ_FAST_READ_QUAD_OUTPUT (QSPI_CR_MDSEL_2) /*!< Fast read quad output mode (data on 4 lines). */
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#define QSPI_READ_FAST_READ_QUAD_IO (QSPI_CR_MDSEL_2 | \
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QSPI_CR_MDSEL_0) /*!< Fast read quad I/O mode (address and data on 4 lines). */
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#define QSPI_READ_CUSTOM_STANDARD_READ (QSPI_CR_MDSEL_2 | \
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QSPI_CR_MDSEL_1) /*!< Custom standard read mode. */
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#define QSPI_READ_CUSTOM_FAST_READ (QSPI_CR_MDSEL_2 | \
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QSPI_CR_MDSEL_1 | \
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QSPI_CR_MDSEL_0) /*!< Custom fast read mode. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_Prefetch_Cmd QSPI Prefetch Cmd
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* @{
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*/
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#define QSPI_PREFETCH_DISABLE (0x0U) /*!< Disable prefetch. */
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#define QSPI_PREFETCH_ENABLE (QSPI_CR_PFE) /*!< Enable prefetch. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_Prefetch_Stop_Position QSPI Prefetch Stop Position
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* @{
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*/
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#define QSPI_PREFETCH_STOP_BYTE_EDGE (0x0U) /*!< Stop prefetch at the edge of byte. */
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#define QSPI_PREFETCH_STOP_IMMED (QSPI_CR_PFSAE) /*!< Stop prefetch at current position immediately. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_Communication_Mode QSPI Communication Mode
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* @{
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*/
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#define QSPI_COMM_ROM_ACCESS (0x0U) /*!< ROM access mode. */
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#define QSPI_COMM_DIRECT_COMM (QSPI_CR_DCOME) /*!< Direct communication mode. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_XIP_Mode_Command QSPI XIP Mode Command
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* @{
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*/
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#define QSPI_XIP_DISABLE (0x0U) /*!< XIP mode disable. */
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#define QSPI_XIP_ENABLE (QSPI_CR_XIPE) /*!< XIP mode enable. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_SPI_Mode QSPI SPI Mode
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* @{
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*/
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#define QSPI_SPI_MODE_0 (0x0U) /*!< Selects SPI mode 0. */
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#define QSPI_SPI_MODE_3 (QSPI_CR_SPIMD3) /*!< Selects SPI mode 3. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_Instruction_Mode QSPI Instruction Mode
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* @{
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*/
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#define QSPI_INSTR_1LINE (0x0U) /*!< Instruction on a single line. */
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#define QSPI_INSTR_2LINE (QSPI_CR_IPRSL_0) /*!< Instruction on 2 lines. */
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#define QSPI_INSTR_4LINE (QSPI_CR_IPRSL_1) /*!< Instruction on 4 lines. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_Addr_Mode QSPI Address Mode
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* @{
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*/
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#define QSPI_ADDR_1LINE (0x0U) /*!< Address on a single line. */
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#define QSPI_ADDR_2LINE (QSPI_CR_APRSL_0) /*!< Address on 2 lines. */
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#define QSPI_ADDR_4LINE (QSPI_CR_APRSL_1) /*!< Address on 4 lines. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_Data_Mode QSPI Data Mode
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* @{
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*/
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#define QSPI_DATA_1LINE (0x0U) /*!< Data on a single line. */
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#define QSPI_DATA_2LINE (QSPI_CR_DPRSL_0) /*!< Data on 2 lines. */
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#define QSPI_DATA_4LINE (QSPI_CR_DPRSL_1) /*!< Data on 4 lines. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_CS_Extend_Time QSPI Chip-select Extend Time
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* @{
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*/
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#define QSPI_CS_EXTEND_0CYCLE (0x0U) /*!< Do not extend chip-select signal time. */
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#define QSPI_CS_EXTEND_32CYCLE (QSPI_CSCR_SSNW_0) /*!< Extend chip-select time by 32 QSCK cycles. */
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#define QSPI_CS_EXTEND_128CYCLE (QSPI_CSCR_SSNW_1) /*!< Extend chip-select time by 128 QSCK cycles. */
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#define QSPI_CS_EXTEND_INFINITE (QSPI_CSCR_SSNW_1 | \
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QSPI_CSCR_SSNW_0) /*!< Extend chip-select time infinitely. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_Addr_Width QSPI Address Width
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* @{
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*/
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#define QSPI_ADDR_WIDTH_1BYTE (0x0U) /*!< QSPI address width is 1 byte. */
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#define QSPI_ADDR_WIDTH_2BYTE (QSPI_FCR_AWSL_0) /*!< QSPI address width is 2 bytes. */
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#define QSPI_ADDR_WIDTH_3BYTE (QSPI_FCR_AWSL_1) /*!< QSPI address width is 3 bytes. */
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#define QSPI_ADDR_WIDTH_4BYTE (QSPI_FCR_AWSL_1 | \
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QSPI_FCR_AWSL_0) /*!< QSPI address width is 4 bytes. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_4BIC_Command QSPI 4-Byte Address Instruction Read Code Command
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* @note Valid when the serial interface address width is 4 bytes.
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* @{
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*/
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#define QSPI_4BIC_DISABLE (0x0U) /*!< Do not use 4-byte address read instruction code. */
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#define QSPI_4BIC_ENABLE (QSPI_FCR_FOUR_BIC) /*!< Use 4-byte address read instruction code. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_CS_Release_Timing QSPI Chip-select Hold Timing
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* @{
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*/
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#define QSPI_CS_RELEASE_AFTER_0P5_CYCLE (0x0U) /*!< Release chip-select signal 0.5 QSCK cycles after the last rising edge of QSCK. */
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#define QSPI_CS_RELEASE_AFTER_1P5_CYCLE (QSPI_FCR_SSNHD) /*!< Release chip-select signal 1.5 QSCK cycles after the last rising edge of QSCK. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_CS_Setup_Timing QSPI Chip-select Setup Timing
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* @{
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*/
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#define QSPI_CS_SETUP_BEFORE_0P5_CYCLE (0x0U) /*!< Output chip-select signal 0.5 QSCK cycles before the first rising edge of QSCK. */
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#define QSPI_CS_SETUP_BEFORE_1P5_CYCLE (QSPI_FCR_SSNLD) /*!< Output chip-select signal 1.5 QSCK cycles before the first rising edge of QSCK. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_WP_Level QSPI Write Protect Pin Level
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* @{
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*/
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#define QSPI_WP_LOW (0x0U) /*!< WP(QIO2) output low. */
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#define QSPI_WP_HIGH (QSPI_FCR_WPOL) /*!< WP(QIO2) output high. */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_QSCK_Duty_Correction_Command QSPI QSCK Duty Correction Command
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* @{
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*/
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#define QSPI_DUTY_CORRECTION_DISABLE (0x0U) /*!< Make no duty ratio correction on QSCK. */
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#define QSPI_DUTY_CORRECTION_ENABLE (QSPI_FCR_DUTY) /*!< Delay the rising of the QSCK signal by 0.5 HCLK cycles. \
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(Valid when HCLK is multiplied by an odd number.) */
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_Status_Flag QSPI Status Flag
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* @{
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*/
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#define QSPI_FLAG_DIRECT_COMM_BUSY (QSPI_SR_BUSY) /*!< Serial transfer being processed. */
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#define QSPI_FLAG_XIP_MODE (QSPI_SR_XIPF) /*!< XIP mode. */
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#define QSPI_FLAG_ROM_ACCESS_ERR (QSPI_SR_RAER) /*!< ROM access detection status in direct communication mode. */
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#define QSPI_FLAG_PREFETCH_BUF_FULL (QSPI_SR_PFFUL) /*!< Prefetch buffer is full. */
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#define QSPI_FLAG_PREFETCH_ACTIVE (QSPI_SR_PFAN) /*!< Prefetch function operating. */
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#define QSPI_FLAG_ALL (QSPI_FLAG_DIRECT_COMM_BUSY | \
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QSPI_FLAG_XIP_MODE | \
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QSPI_FLAG_ROM_ACCESS_ERR | \
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QSPI_FLAG_PREFETCH_BUF_FULL | \
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QSPI_FLAG_PREFETCH_ACTIVE)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/**
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* @addtogroup QSPI_Global_Functions
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* @{
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*/
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/**
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* @brief Enter direct communication mode.
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* @param None
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* @retval None
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*/
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__STATIC_INLINE void QSPI_EnterDirectCommMode(void)
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{
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/* Set standard read mode. */
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CLEAR_REG32_BIT(M4_QSPI->CR, QSPI_CR_MDSEL);
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/* Enter direct communication mode. */
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SET_REG32_BIT(M4_QSPI->CR, QSPI_CR_DCOME);
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}
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/**
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* @brief Exit direct communication mode.
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* @param None
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* @retval None
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*/
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__STATIC_INLINE void QSPI_ExitDirectCommMode(void)
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{
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CLEAR_REG32_BIT(M4_QSPI->CR, QSPI_CR_DCOME);
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}
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/**
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* @brief Write data in direct communication mode.
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* @param [in] u8Val Byte data.
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* @retval None
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*/
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__STATIC_INLINE void QSPI_WriteDirectCommValue(uint8_t u8Val)
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{
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WRITE_REG32(M4_QSPI->DCOM, u8Val);
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}
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/**
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* @brief Read data in communication mode.
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* @param None
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* @retval Byte data.
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*/
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__STATIC_INLINE uint8_t QSPI_ReadDirectCommValue(void)
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{
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return (uint8_t)M4_QSPI->DCOM;
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}
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/**
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* @brief Set ROM access instruction.
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* @param [in] u8Instr ROM access instruction.
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* @retval None
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*/
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__STATIC_INLINE void QSPI_SetRomAccressInstr(uint8_t u8Instr)
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{
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WRITE_REG32(M4_QSPI->CCMD, u8Instr);
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}
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en_result_t QSPI_Init(const stc_qspi_init_t *pstcInit);
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void QSPI_DeInit(void);
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en_result_t QSPI_StructInit(stc_qspi_init_t *pstcInit);
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en_result_t QSPI_WriteData(uint32_t u32Instr, uint32_t u32Address, \
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const uint8_t pu8Src[], uint32_t u32SrcSize);
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en_result_t QSPI_ReadData(uint32_t u32Address, uint8_t pu8Dest[], uint32_t u32DestSize);
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void QSPI_SetReadMode(uint32_t u32ReadMode, uint8_t u8ReadInstr, uint32_t u32DummyCycles);
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void QSPI_DutyCorrectCmd(en_functional_state_t enNewState);
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void QSPI_PrefetchCmd(en_functional_state_t enNewState);
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void QSPI_XIPModeCmd(en_functional_state_t enNewState);
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void QSPI_SetWPPinLevel(uint32_t u32Level);
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void QSPI_4ByteAddrModeCmd(en_functional_state_t enNewState);
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void QSPI_SelectBlock(uint32_t u32Block);
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uint32_t QSPI_GetPrefetchedSize(void);
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en_flag_status_t QSPI_GetStatus(uint32_t u32Flag);
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void QSPI_ClrStatus(uint32_t u32Flag);
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void QSPI_EnterDirectCommMode(void);
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void QSPI_ExitDirectCommMode(void);
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void QSPI_WriteDirectCommValue(uint8_t u8Val);
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uint8_t QSPI_ReadDirectCommValue(void);
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void QSPI_SetRomAccressInstr(uint8_t u8Instr);
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/**
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* @}
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*/
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#endif /* DDL_QSPI_ENABLE */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HC32F4A0_QSPI_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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