196 lines
6.3 KiB
C
196 lines
6.3 KiB
C
/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009 RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2009-01-05 Bernard first implementation
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* 2013-07-12 aozima update for auto initial.
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "stm32f10x.h"
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#include "stm32f10x_fsmc.h"
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#include "board.h"
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#ifdef RT_USING_COMPONENTS_INIT
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#include <components.h>
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#endif /* RT_USING_COMPONENTS_INIT */
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/**
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* @addtogroup STM32
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*/
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/*@{*/
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/*******************************************************************************
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* Function Name : NVIC_Configuration
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* Description : Configures Vector Table base location.
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* Input : None
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* Output : None
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* Return : None
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*******************************************************************************/
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void NVIC_Configuration(void)
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{
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#ifdef VECT_TAB_RAM
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/* Set the Vector Table base location at 0x20000000 */
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NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
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#else /* VECT_TAB_FLASH */
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/* Set the Vector Table base location at 0x08000000 */
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NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
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#endif
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}
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#if STM32_EXT_SRAM
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void EXT_SRAM_Configuration(void)
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{
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FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
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FSMC_NORSRAMTimingInitTypeDef p;
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/* FSMC GPIO configure */
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_GPIOF
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| RCC_APB2Periph_GPIOG, ENABLE);
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RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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/*
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FSMC_D0 ~ FSMC_D3
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PD14 FSMC_D0 PD15 FSMC_D1 PD0 FSMC_D2 PD1 FSMC_D3
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*/
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_14 | GPIO_Pin_15;
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GPIO_Init(GPIOD,&GPIO_InitStructure);
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/*
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FSMC_D4 ~ FSMC_D12
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PE7 ~ PE15 FSMC_D4 ~ FSMC_D12
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*/
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10
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| GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
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GPIO_Init(GPIOE,&GPIO_InitStructure);
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/* FSMC_D13 ~ FSMC_D15 PD8 ~ PD10 */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
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GPIO_Init(GPIOD,&GPIO_InitStructure);
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/*
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FSMC_A0 ~ FSMC_A5 FSMC_A6 ~ FSMC_A9
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PF0 ~ PF5 PF12 ~ PF15
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*/
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3
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| GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
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GPIO_Init(GPIOF,&GPIO_InitStructure);
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/* FSMC_A10 ~ FSMC_A15 PG0 ~ PG5 */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
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GPIO_Init(GPIOG,&GPIO_InitStructure);
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/* FSMC_A16 ~ FSMC_A18 PD11 ~ PD13 */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
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GPIO_Init(GPIOD,&GPIO_InitStructure);
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/* RD-PD4 WR-PD5 */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
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GPIO_Init(GPIOD,&GPIO_InitStructure);
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/* NBL0-PE0 NBL1-PE1 */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
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GPIO_Init(GPIOE,&GPIO_InitStructure);
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/* NE1/NCE2 */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
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GPIO_Init(GPIOD,&GPIO_InitStructure);
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/* NE2 */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
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GPIO_Init(GPIOG,&GPIO_InitStructure);
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/* NE3 */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
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GPIO_Init(GPIOG,&GPIO_InitStructure);
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/* NE4 */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
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GPIO_Init(GPIOG,&GPIO_InitStructure);
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}
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/* FSMC GPIO configure */
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/*-- FSMC Configuration ------------------------------------------------------*/
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p.FSMC_AddressSetupTime = 0;
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p.FSMC_AddressHoldTime = 0;
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p.FSMC_DataSetupTime = 2;
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p.FSMC_BusTurnAroundDuration = 0;
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p.FSMC_CLKDivision = 0;
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p.FSMC_DataLatency = 0;
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p.FSMC_AccessMode = FSMC_AccessMode_A;
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FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
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FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
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FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
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FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
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FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
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FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
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FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
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FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
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FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
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FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
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FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
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FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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/* Enable FSMC Bank1_SRAM Bank */
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FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
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}
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#endif
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/**
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* This is the timer interrupt service routine.
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*
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*/
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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/**
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* This function will initial STM32 board.
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*/
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void rt_hw_board_init(void)
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{
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/* NVIC Configuration */
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NVIC_Configuration();
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/* Configure the SysTick */
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SysTick_Config( SystemCoreClock / RT_TICK_PER_SECOND );
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#if STM32_EXT_SRAM
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EXT_SRAM_Configuration();
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#endif
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rt_hw_usart_init();
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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}
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/*@}*/
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