261 lines
6.7 KiB
C
261 lines
6.7 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "board.h"
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#include <mmu.h>
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/**
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* @addtogroup at91sam9260
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*/
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/*@{*/
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#if defined(__CC_ARM)
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extern int Image$$ER_ZI$$ZI$$Limit;
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#define HEAP_BEGIN (&Image$$ER_ZI$$ZI$$Limit)
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#elif (defined (__GNUC__))
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extern unsigned char __bss_end__;
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#define HEAP_BEGIN (&__bss_end__)
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#elif (defined (__ICCARM__))
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#pragma section=".noinit"
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#define HEAP_BEGIN (__section_end(".noinit"))
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#endif
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#define HEAP_END (((rt_uint32_t)HEAP_BEGIN & (0xF0 << 24)) + (32 << 20))
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extern void rt_hw_interrupt_init(void);
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extern void rt_hw_clock_init(void);
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extern void rt_hw_get_clock(void);
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extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
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extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
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extern void rt_dbgu_isr(void);
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static struct mem_desc at91_mem_desc[] = {
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{ 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */
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{ 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */
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{ 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */
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{ 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */
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{ 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */
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};
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#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
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#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
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static rt_uint32_t pit_cycle; /* write-once */
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static rt_uint32_t pit_cnt; /* access only w/system irq blocked */
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/**
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* This function will handle rtos timer
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*/
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void rt_timer_handler(int vector, void *param)
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{
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#ifdef RT_USING_DBGU
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if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1)
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{
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rt_dbgu_isr();
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}
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#endif
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if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)
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{
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unsigned nr_ticks;
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/* Get number of ticks performed before irq, and ack it */
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nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
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rt_tick_increase();
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}
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}
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static void at91sam926x_pit_reset(void)
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{
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/* Disable timer and irqs */
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at91_sys_write(AT91_PIT_MR, 0);
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/* Clear any pending interrupts, wait for PIT to stop counting */
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while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
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;
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/* Start PIT but don't enable IRQ */
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//at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
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pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
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at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
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| AT91_PIT_PITIEN);
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rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR));
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}
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/*
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* Set up both clocksource and clockevent support.
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*/
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static void at91sam926x_pit_init(void)
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{
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rt_uint32_t pit_rate;
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rt_uint32_t bits;
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/*
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* Use our actual MCK to figure out how many MCK/16 ticks per
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* 1/HZ period (instead of a compile-time constant LATCH).
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*/
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pit_rate = clk_get_rate(clk_get("mck")) / 16;
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rt_kprintf("pit_rate=%dHZ\n", pit_rate);
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pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
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/* Initialize and enable the timer */
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at91sam926x_pit_reset();
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}
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/**
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* This function will init pit for system ticks
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*/
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void rt_hw_timer_init()
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{
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at91sam926x_pit_init();
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/* install interrupt handler */
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rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler,
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RT_NULL, "system");
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rt_hw_interrupt_umask(AT91_ID_SYS);
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}
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void at91_tc1_init()
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{
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at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_TC0);
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writel(AT91_TC_TC0XC0S_NONE | AT91_TC_TC1XC1S_NONE | AT91_TC_TC2XC2S_NONE, AT91SAM9260_BASE_TCB0 + AT91_TC_BMR);
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writel(AT91_TC_CLKDIS, AT91SAM9260_BASE_TC0 + AT91_TC_CCR);
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writel(AT91_TC_TIMER_CLOCK4, AT91SAM9260_BASE_TC0 + AT91_TC_CMR);
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writel(0xffff, AT91SAM9260_BASE_TC0 + AT91_TC_CV);
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}
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#define RXRDY 0x01
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#define TXRDY (1 << 1)
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#define BPS 115200 /* serial baudrate */
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typedef struct uartport
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{
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volatile rt_uint32_t CR;
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volatile rt_uint32_t MR;
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volatile rt_uint32_t IER;
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volatile rt_uint32_t IDR;
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volatile rt_uint32_t IMR;
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volatile rt_uint32_t CSR;
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volatile rt_uint32_t RHR;
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volatile rt_uint32_t THR;
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volatile rt_uint32_t BRGR;
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volatile rt_uint32_t RTOR;
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volatile rt_uint32_t TTGR;
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volatile rt_uint32_t reserved0[5];
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volatile rt_uint32_t FIDI;
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volatile rt_uint32_t NER;
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volatile rt_uint32_t reserved1;
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volatile rt_uint32_t IFR;
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volatile rt_uint32_t reserved2[44];
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volatile rt_uint32_t RPR;
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volatile rt_uint32_t RCR;
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volatile rt_uint32_t TPR;
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volatile rt_uint32_t TCR;
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volatile rt_uint32_t RNPR;
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volatile rt_uint32_t RNCR;
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volatile rt_uint32_t TNPR;
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volatile rt_uint32_t TNCR;
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volatile rt_uint32_t PTCR;
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volatile rt_uint32_t PTSR;
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}uartport;
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#define CIDR FIDI
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#define EXID NER
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#define FNR reserved1
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#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU)
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static void at91_usart_putc(char c)
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{
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while (!(DBGU->CSR & TXRDY));
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DBGU->THR = c;
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}
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/**
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* This function is used to display a string on console, normally, it's
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* invoked by rt_kprintf
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*
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* @param str the displayed string
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*/
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void rt_hw_console_output(const char* str)
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{
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while (*str)
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{
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if (*str=='\n')
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{
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at91_usart_putc('\r');
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}
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at91_usart_putc(*str++);
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}
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}
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static void rt_hw_console_init(void)
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{
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int div;
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int mode = 0;
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DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX |
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AT91_US_RXDIS | AT91_US_TXDIS;
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mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK |
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AT91_US_CHMODE_NORMAL;
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mode |= AT91_US_CHRL_8;
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mode |= AT91_US_NBSTOP_1;
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mode |= AT91_US_PAR_NONE;
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DBGU->MR = mode;
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div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
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DBGU->BRGR = div;
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DBGU->CR = AT91_US_RXEN | AT91_US_TXEN;
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}
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/**
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* This function will init at91sam9260 board
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*/
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void rt_hw_board_init()
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{
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/* initialize the system clock */
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rt_hw_clock_init();
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/* initialize console */
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rt_hw_console_init();
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/* initialize mmu */
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rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
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/* initialize hardware interrupt */
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rt_hw_interrupt_init();
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/* initialize early device */
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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/* initialize timer0 */
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rt_hw_timer_init();
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/* initialize board */
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#ifdef RT_USING_HEAP
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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}
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/*@}*/
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