214 lines
11 KiB
C
214 lines
11 KiB
C
//*****************************************************************************
|
|
//
|
|
// hw_gpio.h - Defines and Macros for GPIO hardware.
|
|
//
|
|
// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved.
|
|
// Software License Agreement
|
|
//
|
|
// Redistribution and use in source and binary forms, with or without
|
|
// modification, are permitted provided that the following conditions
|
|
// are met:
|
|
//
|
|
// Redistributions of source code must retain the above copyright
|
|
// notice, this list of conditions and the following disclaimer.
|
|
//
|
|
// Redistributions in binary form must reproduce the above copyright
|
|
// notice, this list of conditions and the following disclaimer in the
|
|
// documentation and/or other materials provided with the
|
|
// distribution.
|
|
//
|
|
// Neither the name of Texas Instruments Incorporated nor the names of
|
|
// its contributors may be used to endorse or promote products derived
|
|
// from this software without specific prior written permission.
|
|
//
|
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
//
|
|
// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package.
|
|
//
|
|
//*****************************************************************************
|
|
|
|
#ifndef __HW_GPIO_H__
|
|
#define __HW_GPIO_H__
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the GPIO register offsets.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_O_DATA 0x00000000 // GPIO Data
|
|
#define GPIO_O_DIR 0x00000400 // GPIO Direction
|
|
#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense
|
|
#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges
|
|
#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event
|
|
#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask
|
|
#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status
|
|
#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status
|
|
#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear
|
|
#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select
|
|
#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select
|
|
#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select
|
|
#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select
|
|
#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select
|
|
#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select
|
|
#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select
|
|
#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select
|
|
#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable
|
|
#define GPIO_O_LOCK 0x00000520 // GPIO Lock
|
|
#define GPIO_O_CR 0x00000524 // GPIO Commit
|
|
#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
|
|
#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
|
|
#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
|
|
#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
|
|
#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
|
|
#define GPIO_O_DR12R 0x0000053C // GPIO 12-mA Drive Select
|
|
#define GPIO_O_WAKEPEN 0x00000540 // GPIO Wake Pin Enable
|
|
#define GPIO_O_WAKELVL 0x00000544 // GPIO Wake Level
|
|
#define GPIO_O_WAKESTAT 0x00000548 // GPIO Wake Status
|
|
#define GPIO_O_PP 0x00000FC0 // GPIO Peripheral Property
|
|
#define GPIO_O_PC 0x00000FC4 // GPIO Peripheral Configuration
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_IM register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_IM_DMAIME 0x00000100 // GPIO uDMA Done Interrupt Mask
|
|
// Enable
|
|
#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
|
|
#define GPIO_IM_GPIO_S 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_RIS register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_RIS_DMARIS 0x00000100 // GPIO uDMA Done Interrupt Raw
|
|
// Status
|
|
#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
|
|
#define GPIO_RIS_GPIO_S 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_MIS register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_MIS_DMAMIS 0x00000100 // GPIO uDMA Done Masked Interrupt
|
|
// Status
|
|
#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
|
|
#define GPIO_MIS_GPIO_S 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_ICR register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_ICR_DMAIC 0x00000100 // GPIO uDMA Interrupt Clear
|
|
#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
|
|
#define GPIO_ICR_GPIO_S 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_LOCK register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
|
|
#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
|
|
// and may be modified
|
|
#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
|
|
// and may not be modified
|
|
#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_SI register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_DR12R register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_DR12R_DRV12_M 0x000000FF // Output Pad 12-mA Drive Enable
|
|
#define GPIO_DR12R_DRV12_12MA 0x00000001 // The corresponding GPIO pin has
|
|
// 12-mA drive. This encoding is
|
|
// only valid if the GPIOPP EDE bit
|
|
// is set and the appropriate
|
|
// GPIOPC EDM bit field is
|
|
// programmed to 0x3
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_WAKEPEN register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_WAKEPEN_WAKEP4 0x00000010 // P[4] Wake Enable
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_WAKELVL register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_WAKELVL_WAKELVL4 0x00000010 // P[4] Wake Level
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_WAKESTAT
|
|
// register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_WAKESTAT_STAT4 0x00000010 // P[4] Wake Status
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_PP register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_PP_EDE 0x00000001 // Extended Drive Enable
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_PC register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_PC_EDM7_M 0x0000C000 // Extended Drive Mode Bit 7
|
|
#define GPIO_PC_EDM6_M 0x00003000 // Extended Drive Mode Bit 6
|
|
#define GPIO_PC_EDM5_M 0x00000C00 // Extended Drive Mode Bit 5
|
|
#define GPIO_PC_EDM4_M 0x00000300 // Extended Drive Mode Bit 4
|
|
#define GPIO_PC_EDM3_M 0x000000C0 // Extended Drive Mode Bit 3
|
|
#define GPIO_PC_EDM2_M 0x00000030 // Extended Drive Mode Bit 2
|
|
#define GPIO_PC_EDM1_M 0x0000000C // Extended Drive Mode Bit 1
|
|
#define GPIO_PC_EDM0_M 0x00000003 // Extended Drive Mode Bit 0
|
|
#define GPIO_PC_EDM0_DISABLE 0x00000000 // Drive values of 2, 4 and 8 mA
|
|
// are maintained. GPIO n Drive
|
|
// Select (GPIODRnR) registers
|
|
// function as normal
|
|
#define GPIO_PC_EDM0_6MA 0x00000001 // An additional 6 mA option is
|
|
// provided
|
|
#define GPIO_PC_EDM0_PLUS2MA 0x00000003 // A 2 mA driver is always enabled;
|
|
// setting the corresponding
|
|
// GPIODR4R register bit adds 2 mA
|
|
// and setting the corresponding
|
|
// GPIODR8R of GPIODR12R register
|
|
// bit adds an additional 4 mA
|
|
#define GPIO_PC_EDM7_S 14
|
|
#define GPIO_PC_EDM6_S 12
|
|
#define GPIO_PC_EDM5_S 10
|
|
#define GPIO_PC_EDM4_S 8
|
|
#define GPIO_PC_EDM3_S 6
|
|
#define GPIO_PC_EDM2_S 4
|
|
#define GPIO_PC_EDM1_S 2
|
|
|
|
#endif // __HW_GPIO_H__
|