160 lines
3.7 KiB
C
160 lines
3.7 KiB
C
/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-12-04 Jiaxun Yang Initial version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "exception.h"
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#include "mips_regs.h"
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/**
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* @addtogroup MIPS
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*/
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/*@{*/
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extern rt_uint32_t __ebase_entry;
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rt_uint32_t rt_interrupt_from_thread;
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rt_uint32_t rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrupt_flag;
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rt_base_t rt_hw_interrupt_disable(void)
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{
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rt_base_t status = read_c0_status();
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clear_c0_status(ST0_IE);
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return status;
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}
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void rt_hw_interrupt_enable(rt_base_t level)
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{
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write_c0_status(level);
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}
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/**
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* exception handle table
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*/
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#define RT_EXCEPTION_MAX 31
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exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
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/**
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* setup the exception handle
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*/
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exception_func_t rt_set_except_vector(int n, exception_func_t func)
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{
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exception_func_t old_handler = sys_exception_handlers[n];
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if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
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{
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return 0;
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}
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sys_exception_handlers[n] = func;
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return old_handler;
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}
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void mips_dump_regs(struct pt_regs *regs) {
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int i, j;
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for(i = 0; i < 32 / 4; i++) {
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for(j = 0; j < 4; j++) {
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int reg = 4 * i + j;
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rt_kprintf("%d: 0x%08x, ", reg, regs->regs[reg]);
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}
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rt_kprintf("\n");
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}
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}
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void tlb_refill_handler(void)
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{
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rt_kprintf("TLB-Miss Happens, EPC: 0x%08x\n", read_c0_epc());
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rt_hw_cpu_shutdown();
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}
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void cache_error_handler(void)
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{
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rt_kprintf("Cache Exception Happens, EPC: 0x%08x\n", read_c0_epc());
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rt_hw_cpu_shutdown();
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}
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static void unhandled_exception_handle(struct pt_regs *regs)
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{
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rt_kprintf("Unknown Exception, EPC: 0x%08x, CAUSE: 0x%08x\n", read_c0_epc(), read_c0_cause());
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rt_kprintf("ST0: 0x%08x ",regs->cp0_status);
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rt_kprintf("ErrorPC: 0x%08x\n",read_c0_errorepc());
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mips_dump_regs(regs);
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rt_hw_cpu_shutdown();
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}
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static void install_default_exception_handler(void)
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{
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rt_int32_t i;
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for (i=0; i<RT_EXCEPTION_MAX; i++)
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sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
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}
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int rt_hw_exception_init(void)
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{
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rt_uint32_t ebase = (rt_uint32_t)&__ebase_entry;
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write_c0_ebase(ebase);
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clear_c0_status(ST0_BEV | ST0_ERL | ST0_EXL);
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clear_c0_status(ST0_IM | ST0_IE);
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set_c0_status(ST0_CU0);
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/* install the default exception handler */
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install_default_exception_handler();
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return RT_EOK;
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}
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void rt_general_exc_dispatch(struct pt_regs *regs)
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{
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rt_uint32_t cause, exccode;
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exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
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if (exccode == 0) {
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rt_uint32_t status, pending;
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status = read_c0_status();
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pending = (cause & CAUSEF_IP) & (status & ST0_IM);
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if (pending & CAUSEF_IP0)
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rt_do_mips_cpu_irq(0);
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if (pending & CAUSEF_IP1)
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rt_do_mips_cpu_irq(1);
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if (pending & CAUSEF_IP2)
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rt_do_mips_cpu_irq(2);
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if (pending & CAUSEF_IP3)
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rt_do_mips_cpu_irq(3);
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if (pending & CAUSEF_IP4)
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rt_do_mips_cpu_irq(4);
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if (pending & CAUSEF_IP5)
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rt_do_mips_cpu_irq(5);
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if (pending & CAUSEF_IP6)
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rt_do_mips_cpu_irq(6);
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if (pending & CAUSEF_IP7)
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rt_do_mips_cpu_irq(7);
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} else {
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if (sys_exception_handlers[exccode])
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sys_exception_handlers[exccode](regs);
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}
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}
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/* Mask means disable the interrupt */
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void mips_mask_cpu_irq(rt_uint32_t irq)
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{
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clear_c0_status(1 << (STATUSB_IP0 + irq));
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}
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/* Unmask means enable the interrupt */
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void mips_unmask_cpu_irq(rt_uint32_t irq)
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{
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set_c0_status(1 << (STATUSB_IP0 + irq));
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}
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/*@}*/
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