204 lines
5.5 KiB
C
204 lines
5.5 KiB
C
/*""FILE COMMENT""*******************************************************
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* System Name : Serial Communication Interface API for RX62Nxx
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* File Name : r_pdl_sci.h
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* Version : 1.02
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* Contents : Serial Interface API header
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* Customer :
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* Model :
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* Order :
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* CPU : RX
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* Compiler : RXC
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* OS : Nothing
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* Programmer :
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* Note :
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************************************************************************
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* Copyright, 2011. Renesas Electronics Corporation
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* and Renesas Solutions Corporation
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************************************************************************
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* History : 2011.04.08
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* : Ver 1.02
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* : CS-5 release.
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*""FILE COMMENT END""**************************************************/
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#ifndef R_PDL_SCI_H
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#define R_PDL_SCI_H
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#include "r_pdl_common_defs_RX62Nxx.h"
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/* Function prototypes */
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bool R_SCI_Set(
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uint8_t
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);
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bool R_SCI_Create(
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uint8_t,
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uint32_t,
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uint32_t,
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uint8_t
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);
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bool R_SCI_Destroy(
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uint8_t
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);
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bool R_SCI_Send(
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uint8_t,
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uint16_t,
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uint8_t *,
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uint16_t,
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void *
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);
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bool R_SCI_Receive(
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uint8_t,
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uint16_t,
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uint8_t *,
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uint16_t,
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void *,
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void *
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);
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bool R_SCI_Control(
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uint8_t,
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uint8_t
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);
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bool R_SCI_GetStatus(
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uint8_t,
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uint8_t *,
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uint8_t *,
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uint16_t *,
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uint16_t *
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);
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/* ------------------------ */
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/* R_SCI_Set, Configuration */
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/* ------------------------ */
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/* Pin selection */
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#define PDL_SCI_PIN_SCI1_A 0x01u
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#define PDL_SCI_PIN_SCI1_B 0x02u
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#define PDL_SCI_PIN_SCI2_A 0x04u
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#define PDL_SCI_PIN_SCI2_B 0x08u
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#define PDL_SCI_PIN_SCI3_A 0x10u
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#define PDL_SCI_PIN_SCI3_B 0x20u
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#define PDL_SCI_PIN_SCI6_A 0x40u
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#define PDL_SCI_PIN_SCI6_B 0x80u
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/* ----------------------------------------- */
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/* R_SCI_Create, data2 Channel configuration */
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/* ----------------------------------------- */
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/* Operation mode */
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#define PDL_SCI_ASYNC 0x00000001ul
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#define PDL_SCI_SYNC 0x00000002ul
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#define PDL_SCI_SMART 0x00000004ul
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#define PDL_SCI_ASYNC_MP 0x00000008ul
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/* Common selections */
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/* Transmit / Receive connections */
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#define PDL_SCI_TX_CONNECTED 0x00000010ul
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#define PDL_SCI_TX_DISCONNECTED 0x00000020ul
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#define PDL_SCI_RX_CONNECTED 0x00000040ul
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#define PDL_SCI_RX_DISCONNECTED 0x00000080ul
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/* Data clock source */
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#define PDL_SCI_CLK_INT_OUT 0x00000100ul
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#define PDL_SCI_CLK_EXT 0x00000200ul
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/* Parity selection */
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#define PDL_SCI_PARITY_EVEN 0x00000400ul
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#define PDL_SCI_PARITY_ODD 0x00000800ul
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/* Asynchronous-only selections */
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/* Data clock source */
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#define PDL_SCI_CLK_INT_IO 0x00001000ul
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#define PDL_SCI_CLK_TMR 0x00002000ul
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/* Data length */
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#define PDL_SCI_8_BIT_LENGTH 0x00004000ul
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#define PDL_SCI_7_BIT_LENGTH 0x00008000ul
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/* Parity selection */
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#define PDL_SCI_PARITY_NONE 0x00010000ul
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/* Stop bit length */
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#define PDL_SCI_STOP_1 0x00020000ul
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#define PDL_SCI_STOP_2 0x00040000ul
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#define PDL_SCI_8N1 (PDL_SCI_8_BIT_LENGTH | PDL_SCI_PARITY_NONE | PDL_SCI_STOP_1)
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/* Smart card-only selections */
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/* Data transfer format */
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#define PDL_SCI_LSB_FIRST 0x00001000ul
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#define PDL_SCI_MSB_FIRST 0x00002000ul
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/* Data inversion */
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#define PDL_SCI_INVERSION_OFF 0x00004000ul
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#define PDL_SCI_INVERSION_ON 0x00008000ul
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/* Base clock pulse cycle count */
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#define PDL_SCI_BCP_32 0x00010000ul
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#define PDL_SCI_BCP_64 0x00020000ul
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#define PDL_SCI_BCP_93 0x00040000ul
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#define PDL_SCI_BCP_128 0x00080000ul
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#define PDL_SCI_BCP_186 0x00100000ul
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#define PDL_SCI_BCP_256 0x00200000ul
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#define PDL_SCI_BCP_372 0x00400000ul
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#define PDL_SCI_BCP_512 0x00800000ul
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/* Block transfer mode */
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#define PDL_SCI_BLOCK_MODE_OFF 0x01000000ul
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#define PDL_SCI_BLOCK_MODE_ON 0x02000000ul
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/* GSM mode */
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#define PDL_SCI_GSM_MODE_OFF 0x04000000ul
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#define PDL_SCI_GSM_MODE_ON 0x08000000ul
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/* Clock output control */
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#define PDL_SCI_SCK_OUTPUT_OFF 0x10000000ul
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#define PDL_SCI_SCK_OUTPUT_LOW 0x20000000ul
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#define PDL_SCI_SCK_OUTPUT_ON 0x40000000ul
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#define PDL_SCI_SCK_OUTPUT_HIGH 0x80000000ul
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/* ----------------------------------- */
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/* R_SCI_Create, data3 register value */
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/* ----------------------------------- */
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/* Transfer clock control */
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/* CKS selection (optional) */
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#define PDL_SCI_PCLK_DIV_1 0x01000000ul
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#define PDL_SCI_PCLK_DIV_4 0x02000000ul
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#define PDL_SCI_PCLK_DIV_16 0x03000000ul
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#define PDL_SCI_PCLK_DIV_64 0x04000000ul
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/* ABCS selection (optional) */
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#define PDL_SCI_CYCLE_BIT_16 0x10000000ul
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#define PDL_SCI_CYCLE_BIT_8 0x20000000ul
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/* ----------------------------------------------- */
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/* R_SCI_Send/R_SCI_Receive, Channel configuration */
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/* ----------------------------------------------- */
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/* DMAC / DTC trigger control */
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#define PDL_SCI_DMAC_DTC_TRIGGER_DISABLE 0x0001u
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#define PDL_SCI_DMAC_TRIGGER_ENABLE 0x0002u
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#define PDL_SCI_DTC_TRIGGER_ENABLE 0x0004u
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#define PDL_SCI_MP_ID_CYCLE 0x0008u
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/* ------------------------------ */
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/* R_SCI_Control, Channel control */
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/* ------------------------------ */
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/* Stop control */
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#define PDL_SCI_STOP_TX 0x01u
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#define PDL_SCI_STOP_RX 0x02u
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#define PDL_SCI_STOP_TX_AND_RX (PDL_SCI_STOP_TX | PDL_SCI_STOP_RX)
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/* Break output control */
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#define PDL_SCI_OUTPUT_MARK 0x04u
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#define PDL_SCI_OUTPUT_SPACE 0x08u
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/* Error flag control */
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#define PDL_SCI_CLEAR_RECEIVE_ERROR_FLAGS 0x10u
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/* Manual SCK control */
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#define PDL_SCI_GSM_SCK_STOP 0x20u
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#define PDL_SCI_GSM_SCK_START 0x40u
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#endif
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/* End of file */
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