109 lines
4.4 KiB
C
109 lines
4.4 KiB
C
/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdint.h>
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#include "fsl_common.h"
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#include "clock_config.h"
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#include "board.h"
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#include "fsl_debug_console.h"
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#ifdef SDK_PRIMARY_CORE
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/* Address of RAM, where the image for core1 should be copied */
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#define CORE1_BOOT_ADDRESS (void *)0x20010000
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#if defined(__CC_ARM)
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extern uint32_t Image$$CORE1_REGION$$Base;
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extern uint32_t Image$$CORE1_REGION$$Length;
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#define CORE1_IMAGE_START &Image$$CORE1_REGION$$Base
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#elif defined(__ICCARM__)
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extern unsigned char core1_image_start[];
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#define CORE1_IMAGE_START core1_image_start
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#endif
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#endif
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* Clock rate on the CLKIN pin */
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const uint32_t ExtClockIn = BOARD_EXTCLKINRATE;
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/*******************************************************************************
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* Code
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******************************************************************************/
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/* Initialize debug console. */
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status_t BOARD_InitDebugConsole(void)
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{
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status_t result;
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/* attach 12 MHz clock to FLEXCOMM0 (debug console) */
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CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
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RESET_PeripheralReset(BOARD_DEBUG_UART_RST);
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result = DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM,
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BOARD_DEBUG_UART_CLK_FREQ);
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assert(kStatus_Success == result);
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return result;
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}
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#ifdef SDK_PRIMARY_CORE
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/* Start the secondary core. */
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void BOARD_StartSecondaryCore(void)
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{
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/* Calculate size of the secondary core image - not required on MCUXpresso. MCUXpresso copies the image to RAM during
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* startup
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* automatically */
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#if (defined(__CC_ARM) || defined(__ICCARM__))
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#if defined(__CC_ARM)
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uint32_t core1_image_size = (uint32_t)&Image$$CORE1_REGION$$Length;
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#elif defined(__ICCARM__)
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#pragma section = "__sec_core"
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uint32_t core1_image_size = (uint32_t)__section_end("__sec_core") - (uint32_t)&core1_image_start;
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#endif
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/* Copy core1 application from FLASH to RAM. Primary core code is executed from FLASH, Secondary from RAM
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* for maximal effectivity.*/
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memcpy(CORE1_BOOT_ADDRESS, (void *)CORE1_IMAGE_START, core1_image_size);
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#endif
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/* Boot source for Core 1 from RAM */
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SYSCON->CPBOOT = SYSCON_CPBOOT_BOOTADDR(*(uint32_t *)((uint8_t *)CORE1_BOOT_ADDRESS + 0x4));
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SYSCON->CPSTACK = SYSCON_CPSTACK_STACKADDR(*(uint32_t *)CORE1_BOOT_ADDRESS);
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uint32_t temp = SYSCON->CPUCTRL;
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temp |= 0xc0c48000U;
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SYSCON->CPUCTRL = temp | SYSCON_CPUCTRL_CM0RSTEN_MASK | SYSCON_CPUCTRL_CM0CLKEN_MASK;
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SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CM0CLKEN_MASK) & (~SYSCON_CPUCTRL_CM0RSTEN_MASK);
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}
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#endif
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