66 lines
2.0 KiB
C
66 lines
2.0 KiB
C
/** @file reg_pbist.h
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* @brief PBIST Register Layer Header File
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* @date 29.May.2013
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* @version 03.05.02
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*
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* This file contains:
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* - Definitions
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* - Types
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* .
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* which are relevant for the System driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_PBIST_H__
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#define __REG_PBIST_H__
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#include "sys_common.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* PBIST Register Frame Definition */
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/** @struct pbistBase
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* @brief PBIST Base Register Definition
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*
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* This structure is used to access the PBIST module registers.
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*/
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/** @typedef pbistBASE_t
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* @brief PBIST Register Frame Type Definition
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*
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* This type is used to access the PBIST Registers.
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*/
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typedef volatile struct pbistBase
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{
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uint32 RAMT; /* 0x0160: RAM Configuration Register */
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uint32 DLR; /* 0x0164: Datalogger Register */
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uint32 rsvd1[6U]; /* 0x0168 */
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uint32 PACT; /* 0x0180: PBIST Activate Register */
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uint32 PBISTID; /* 0x0184: PBIST ID Register */
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uint32 OVER; /* 0x0188: Override Register */
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uint32 rsvd2; /* 0x018C */
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uint32 FSRF0; /* 0x0190: Fail Status Fail Register 0 */
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uint32 FSRF1; /* 0x0194: Fail Status Fail Register 1 */
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uint32 FSRC0; /* 0x0198: Fail Status Count Register 0 */
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uint32 FSRC1; /* 0x019C: Fail Status Count Register 1 */
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uint32 FSRA0; /* 0x01A0: Fail Status Address 0 Register */
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uint32 FSRA1; /* 0x01A4: Fail Status Address 1 Register */
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uint32 FSRDL0; /* 0x01A8: Fail Status Data Register 0 */
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uint32 rsvd3; /* 0x01AC */
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uint32 FSRDL1; /* 0x01B0: Fail Status Data Register 1 */
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uint32 rsvd4[3U]; /* 0x01B4 */
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uint32 ROM; /* 0x01C0: ROM Mask Register */
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uint32 ALGO; /* 0x01C4: Algorithm Mask Register */
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uint32 RINFOL; /* 0x01C8: RAM Info Mask Lower Register */
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uint32 RINFOU; /* 0x01CC: RAM Info Mask Upper Register */
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} pbistBASE_t;
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#define pbistREG ((pbistBASE_t *)0xFFFFE560U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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