142 lines
4.1 KiB
C
142 lines
4.1 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2017-2021 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_iee.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.iee"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*!
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* brief Resets IEE module to factory default values.
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*
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* This function performs hardware reset of IEE module. Attributes and keys of all regions are cleared.
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*
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* param base IEER peripheral address.
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*/
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void IEE_Init(IEE_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable IEE clock. */
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CLOCK_EnableClock(kCLOCK_Iee);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Reset IEE module and wait the reset operation done. */
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base->GCFG |= IEE_GCFG_RST_MASK;
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}
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/*!
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* brief Loads default values to the IEE configuration structure.
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*
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* Loads default values to the IEE region configuration structure. The default values are as follows.
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* code
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* config->bypass = kIEE_AesUseMdField;
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* config->mode = kIEE_ModeNone;
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* config->keySize = kIEE_AesCTR128XTS256;
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* config->pageOffset = 0U;
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* endcode
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*
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* param config Configuration for the selected IEE region.
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*/
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void IEE_GetDefaultConfig(iee_config_t *config)
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{
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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config->bypass = kIEE_AesUseMdField;
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config->mode = kIEE_ModeNone;
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config->keySize = kIEE_AesCTR128XTS256;
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config->pageOffset = 0U;
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}
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/*!
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* brief Sets the IEE module according to the configuration structure.
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*
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* This function configures IEE region according to configuration structure.
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*
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* param base IEE peripheral address.
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* param region Selection of the IEE region to be configured.
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* param config Configuration for the selected IEE region.
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*/
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void IEE_SetRegionConfig(IEE_Type *base, iee_region_t region, iee_config_t *config)
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{
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base->REGX[region].REGATTR =
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IEE_REGATTR_BYP(config->bypass) | IEE_REGATTR_MD(config->mode) | IEE_REGATTR_KS(config->keySize);
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#if (defined(FSL_IEE_USE_PAGE_OFFSET) && (FSL_IEE_USE_PAGE_OFFSET > 0U))
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base->REGX[region].REGPO = IEE_REGPO_PGOFF(config->pageOffset);
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#endif /* FSL_IEE_USE_PAGE_OFFSET */
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}
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/*!
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* brief Sets the IEE module key.
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*
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* This function sets specified AES key for the given region.
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*
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* param base IEE peripheral address.
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* param region Selection of the IEE region to be configured.
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* param keyNum Selection of AES KEY1 or KEY2.
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* param key AES key.
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* param keySize Size of AES key.
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*/
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status_t IEE_SetRegionKey(
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IEE_Type *base, iee_region_t region, iee_aes_key_num_t keyNum, const uint8_t *key, size_t keySize)
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{
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register const uint32_t *from32 = (const uint32_t *)(uintptr_t)key;
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register volatile uint32_t *to32 = NULL;
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if (keyNum == kIEE_AesKey1)
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{
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to32 = &base->REGX[region].REGKEY1[0];
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}
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else if (keyNum == kIEE_AesKey2)
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{
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to32 = &base->REGX[region].REGKEY2[0];
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}
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else
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{
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return kStatus_InvalidArgument;
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}
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while (keySize >= sizeof(uint32_t))
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{
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*to32 = *from32;
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keySize -= sizeof(uint32_t);
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from32++;
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to32++;
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}
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return kStatus_Success;
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}
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/*!
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* brief Lock the IEE region configuration.
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*
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* IEE region Key, Offset and Attribute registers are locked.
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* Only system reset can clear the Lock bit.
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*
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* param base IEE peripheral address.
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* param region Selection of the IEE region to be locked.
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*/
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void IEE_LockRegionConfig(IEE_Type *base, iee_region_t region)
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{
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base->GCFG |= (uint32_t)(0x1UL << (uint32_t)region);
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}
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