178 lines
4.2 KiB
C
178 lines
4.2 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-05-18 Bernard The first version for LPC40xx
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* 2019-05-05 jg1uaa port to LPC1114
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*/
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#include <stddef.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <rthw.h>
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#include "board.h" // CPU_CLOCK
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#include "drv_uart.h"
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#ifdef RT_USING_SERIAL
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#define UART_BASE 0x40008000 // UART (only one)
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#define UART_IRQ 21
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#define UART_CLOCK (CPU_CLOCK / 1) // Hz
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#define URBR HWREG32(UART_BASE + 0x00) // R-
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#define UTHR HWREG32(UART_BASE + 0x00) // -W
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#define UIER HWREG32(UART_BASE + 0x04) // RW
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#define UIIR HWREG32(UART_BASE + 0x08) // R-
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#define UFCR HWREG32(UART_BASE + 0x08) // -W
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#define ULCR HWREG32(UART_BASE + 0x0c) // RW
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#define UMCR HWREG32(UART_BASE + 0x10) // RW
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#define ULSR HWREG32(UART_BASE + 0x14) // R-
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#define UMSR HWREG32(UART_BASE + 0x18) // R-
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#define UDLL HWREG32(UART_BASE + 0x00) // RW
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#define UDLM HWREG32(UART_BASE + 0x04) // RW
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#define IOCONFIG_BASE 0x40044000
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#define IOCON_PIO1_6 HWREG32(IOCONFIG_BASE + 0xa4)
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#define IOCON_PIO1_7 HWREG32(IOCONFIG_BASE + 0xa8)
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#define SYSCON_BASE 0x40048000
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#define AHBCLKCTRL HWREG32(SYSCON_BASE + 0x80)
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#define UARTCLKDIV HWREG32(SYSCON_BASE + 0x98)
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static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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rt_uint32_t Fdiv = 0;
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RT_ASSERT(serial != RT_NULL);
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/* Initialize UART Configuration parameter structure to default state:
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* Baudrate = 115200 bps
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* 8 data bit
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* 1 Stop bit
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* None parity
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*/
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/* set DLAB=1 */
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ULCR |= 0x80;
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/* config uart baudrate */
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Fdiv = UART_CLOCK / (cfg->baud_rate * 16);
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UDLM = Fdiv / 256;
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UDLL = Fdiv % 256;
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/* set DLAB=0 */
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ULCR &= ~0x80;
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/* config to 8 data bit,1 Stop bit,None parity */
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ULCR |= 0x03;
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/*enable and reset FIFO*/
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UFCR = 0x07;
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return RT_EOK;
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}
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static rt_err_t lpc_control(struct rt_serial_device *serial, int cmd, void *arg)
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{
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RT_ASSERT(serial != RT_NULL);
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switch (cmd)
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{
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case RT_DEVICE_CTRL_CLR_INT:
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/* disable rx irq */
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UIER &= ~0x01;
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break;
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case RT_DEVICE_CTRL_SET_INT:
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/* enable rx irq */
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UIER |= 0x01;
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break;
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}
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return RT_EOK;
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}
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static int lpc_putc(struct rt_serial_device *serial, char c)
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{
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while (!(ULSR & 0x20));
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UTHR = c;
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return 1;
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}
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static int lpc_getc(struct rt_serial_device *serial)
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{
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if (ULSR & 0x01)
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return URBR;
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else
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return -1;
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}
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static const struct rt_uart_ops lpc_uart_ops =
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{
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lpc_configure,
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lpc_control,
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lpc_putc,
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lpc_getc,
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};
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struct rt_serial_device serial;
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void UART_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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switch (UIIR & 0x0e)
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{
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case 0x04:
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case 0x0C:
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rt_hw_serial_isr(&serial, RT_SERIAL_EVENT_RX_IND);
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break;
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case 0x06:
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(void)ULSR;
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break;
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default:
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(void)ULSR;
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break;
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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int rt_hw_uart_init(void)
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{
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rt_err_t ret = RT_EOK;
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struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
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serial.ops = &lpc_uart_ops;
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serial.config = config;
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serial.parent.user_data = NULL;
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/*
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* Initialize UART pin connect
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* P1.6: U0_RXD
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* P1.7: U0_TXD
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*/
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IOCON_PIO1_6 = 0xc1;
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IOCON_PIO1_7 = 0xc1;
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/* setup the uart power and clock */
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UARTCLKDIV = 0x01; // UART PCLK = system clock / 1
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AHBCLKCTRL |= (1 << 12); // UART power-up
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/* priority = 1 */
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NVIC_SetPriority(UART_IRQ, 0x01 << 6);
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/* Enable Interrupt for UART channel */
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NVIC_EnableIRQ(UART_IRQ);
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/* register UART device */
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ret = rt_hw_serial_register(&serial, "uart",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
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NULL);
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return ret;
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}
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INIT_BOARD_EXPORT(rt_hw_uart_init);
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#endif /* RT_USING_SERIAL */
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