154 lines
3.5 KiB
C
154 lines
3.5 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-04-29 supperthomas first version
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*
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*/
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#include <stdint.h>
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#include "board.h"
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#include "nrfx_qspi.h"
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#if defined(RT_USING_FAL)
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#include <fal.h>
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//log
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#include <rtdbg.h>
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#define LOG_TAG "drv.qspiflash"
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#define WAIT_FOR_PERIPH() do { \
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while (!m_finished) {} \
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m_finished = false; \
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} while (0)
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static volatile bool m_finished = false;
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static void qspi_handler(nrfx_qspi_evt_t event, void *p_context)
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{
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m_finished = true;
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}
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static void configure_memory()
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{
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#define QSPI_STD_CMD_WRSR 0x01
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#define QSPI_STD_CMD_RSTEN 0x66
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#define QSPI_STD_CMD_RST 0x99
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uint8_t temporary = 0x40;
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uint32_t err_code;
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nrf_qspi_cinstr_conf_t cinstr_cfg =
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{
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.opcode = QSPI_STD_CMD_RSTEN,
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.length = NRF_QSPI_CINSTR_LEN_1B,
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.io2_level = true,
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.io3_level = true,
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.wipwait = true,
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.wren = true
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};
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// Send reset enable
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err_code = nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
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if (NRFX_SUCCESS != err_code)
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{
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LOG_E("\r\n ERROR: QSPI_STD_CMD_RSTEN:0x%x\n", err_code);
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return ;
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}
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// Send reset command
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cinstr_cfg.opcode = QSPI_STD_CMD_RST;
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err_code = nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
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if (NRFX_SUCCESS != err_code)
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{
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LOG_E("\r\n ERROR: QSPI_STD_CMD_RST:0x%x\n", err_code);
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return ;
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}
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// Switch to qspi mode
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cinstr_cfg.opcode = QSPI_STD_CMD_WRSR;
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cinstr_cfg.length = NRF_QSPI_CINSTR_LEN_2B;
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err_code = nrfx_qspi_cinstr_xfer(&cinstr_cfg, &temporary, NULL);
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if (NRFX_SUCCESS != err_code)
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{
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LOG_E("\r\n ERROR: QSPI_STD_CMD_WRSR:0x%x\n", err_code);
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return;
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}
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}
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static int init(void)
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{
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uint32_t err_code;
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nrfx_qspi_config_t config = NRFX_QSPI_DEFAULT_CONFIG(BSP_QSPI_SCK_PIN, BSP_QSPI_CSN_PIN,
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BSP_QSPI_IO0_PIN, BSP_QSPI_IO1_PIN, BSP_QSPI_IO2_PIN, BSP_QSPI_IO3_PIN);
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err_code = nrfx_qspi_init(&config, qspi_handler, NULL);
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if (NRFX_SUCCESS != err_code)
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{
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LOG_E("\r\n ERROR: QSPI_init:0x%x\n", err_code);
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return -1;
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}
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configure_memory();
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return 0;
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}
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static int read(long offset, uint8_t *buf, size_t size)
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{
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uint32_t err_code;
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m_finished = false;
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err_code = nrfx_qspi_read(buf, size, offset);
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WAIT_FOR_PERIPH();
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if (NRFX_SUCCESS == err_code)
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{
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return size;
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}
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else
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{
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LOG_E("\r\n ERROR: read:0x%x\n", err_code);
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return -1;
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}
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}
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static int write(long offset, const uint8_t *buf, size_t size)
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{
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uint32_t err_code;
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m_finished = false;
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err_code = nrfx_qspi_write(buf, size, offset);
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WAIT_FOR_PERIPH();
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if (NRFX_SUCCESS == err_code)
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{
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return size;
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}
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else
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{
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LOG_E("\r\n ERROR: write:0x%x\n", err_code);
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return -1;
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}
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}
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static int erase(long offset, size_t size)
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{
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uint32_t err_code;
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m_finished = false;
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err_code = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_64KB, offset);
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WAIT_FOR_PERIPH();
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if (NRFX_SUCCESS == err_code)
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{
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return size;
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}
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else
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{
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LOG_E("\r\n ERROR: erase:0x%x\n", err_code);
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return -1;
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}
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}
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struct fal_flash_dev nor_flash0 =
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{
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.name = NOR_FLASH_DEV_NAME,
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.addr = 0,
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.len = QSPI_FLASH_SIZE_KB * 1024,
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.blk_size = 4096,
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.ops = {init, read, write, erase},
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.write_gran = 1
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};
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#endif
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