93 lines
3.3 KiB
C
93 lines
3.3 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef __RT_HW_CPU_H__
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#define __RT_HW_CPU_H__
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#include <rtdef.h>
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#include <cpuport.h>
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#include <mm_aspace.h>
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#ifdef RT_USING_OFW
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#include <drivers/ofw.h>
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#endif
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#define ID_ERROR __INT64_MAX__
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#define MPIDR_AFFINITY_MASK 0x000000ff00ffffffUL
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struct cpu_ops_t
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{
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const char *method;
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int (*cpu_init)(rt_uint32_t id, void *param);
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int (*cpu_boot)(rt_uint32_t id, rt_uint64_t entry);
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void (*cpu_shutdown)(void);
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};
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#define sysreg_32(op1, crn, crm, op2) s3_##op1 ##_##crn ##_##crm ##_##op2
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#define sysreg_64(op1, crn, crm, op2) sysreg_32(op1, crn, crm, op2)
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#define MPIDR_AFFINITY_MASK 0x000000ff00ffffffUL
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#define MPIDR_LEVEL_BITS_SHIFT 3
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#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
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#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
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#define MPIDR_LEVEL_SHIFT(level) (((1 << (level)) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
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#define MPIDR_AFFINITY_LEVEL(mpidr, level) (((mpidr) >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
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/* GIC registers */
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#define ICC_IAR0_SYS sysreg_64(0, c12, c8, 0)
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#define ICC_IAR1_SYS sysreg_64(0, c12, c12, 0)
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#define ICC_EOIR0_SYS sysreg_64(0, c12, c8, 1)
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#define ICC_EOIR1_SYS sysreg_64(0, c12, c12, 1)
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#define ICC_HPPIR0_SYS sysreg_64(0, c12, c8, 2)
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#define ICC_HPPIR1_SYS sysreg_64(0, c12, c12, 2)
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#define ICC_BPR0_SYS sysreg_64(0, c12, c8, 3)
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#define ICC_BPR1_SYS sysreg_64(0, c12, c12, 3)
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#define ICC_DIR_SYS sysreg_64(0, c12, c11, 1)
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#define ICC_PMR_SYS sysreg_64(0, c4, c6, 0)
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#define ICC_RPR_SYS sysreg_64(0, c12, c11, 3)
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#define ICC_CTLR_SYS sysreg_64(0, c12, c12, 4)
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#define ICC_SRE_SYS sysreg_64(0, c12, c12, 5)
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#define ICC_IGRPEN0_SYS sysreg_64(0, c12, c12, 6)
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#define ICC_IGRPEN1_SYS sysreg_64(0, c12, c12, 7)
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#define ICC_SGI0R_SYS sysreg_64(0, c12, c11, 7)
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#define ICC_SGI1R_SYS sysreg_64(0, c12, c11, 5)
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#define ICC_ASGI1R_SYS sysreg_64(0, c12, c11, 6)
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/* Arch timer registers */
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#define CNTP_CTL CNTP_CTL_EL0 /* EL1 Physical Timer */
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#define CNTHP_CTL CNTHP_CTL_EL2 /* EL2 Non-secure Physical Timer */
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#define CNTHPS_CTL CNTHPS_CTL_EL2 /* EL2 Secure Physical Timer */
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#define CNTPS_CTL CNTPS_CTL_EL1 /* EL3 Physical Timer */
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#define CNTV_CTL CNTV_CTL_EL0 /* EL1 Virtual Timer */
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#define CNTHV_CTL CNTHV_CTL_EL2 /* EL2 Non-secure Virtual Timer */
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#define CNTHVS_CTL CNTHVS_CTL_EL2 /* EL2 Secure Virtual Timer */
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#define CNTP_CVAL CNTP_CVAL_EL0
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#define CNTHP_CVAL CNTHP_CVAL_EL2
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#define CNTHPS_CVAL CNTHPS_CVAL_EL2
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#define CNTPS_CVAL CNTPS_CVAL_EL1
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#define CNTV_CVAL CNTV_CVAL_EL0
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#define CNTHV_CVAL CNTHV_CVAL_EL2
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#define CNTHVS_CVAL CNTHVS_CVAL_EL2
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#define CNTP_TVAL CNTP_TVAL_EL0
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#define CNTHP_TVAL CNTHP_TVAL_EL2
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#define CNTHPS_TVAL CNTHPS_TVAL_EL2
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#define CNTPS_TVAL CNTPS_TVAL_EL1
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#define CNTV_TVAL CNTV_TVAL_EL0
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#define CNTHV_TVAL CNTHV_TVAL_EL2
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#define CNTHVS_TVAL CNTHVS_TVAL_EL2
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#define CNTPCT CNTPCT_EL0
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#define CNTVCT CNTVCT_EL0
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#define CNTFRQ CNTFRQ_EL0
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extern rt_uint64_t rt_cpu_mpidr_table[];
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#endif /* __RT_HW_CPU_H__ */
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